arm64: dts: qcom: sm6350: Add GCC node

Add and configure GCC node to allow for referencing GCC-controlled clocks
in other nodes.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-5-konrad.dybcio@somainline.org

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 555ae0bbba1873720c7211b19de14359f2947745..9934ecec1bb21365c2383eca316c5a9771efff5e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -3,6 +3,8 @@
  * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
  */
 
+#include <dt-bindings/clock/qcom,gcc-sm6350.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -357,6 +359,20 @@
                dma-ranges = <0 0 0 0 0x10 0>;
                compatible = "simple-bus";
 
+               gcc: clock-controller@100000 {
+                       compatible = "qcom,gcc-sm6350";
+                       reg = <0 0x00100000 0 0x1f0000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+                       clock-names = "bi_tcxo",
+                                     "bi_tcxo_ao",
+                                     "sleep_clk";
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK_A>,
+                                <&sleep_clk>;
+               };
+
                ipcc: mailbox@408000 {
                        compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
                        reg = <0 0x00408000 0 0x1000>;