]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
powerpc/64s: Remove TM from Power10 features
authorJordan Niethe <jniethe5@gmail.com>
Thu, 27 Aug 2020 03:55:29 +0000 (13:55 +1000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 29 Oct 2020 09:12:06 +0000 (10:12 +0100)
[ Upstream commit ec613a57fa1d57381f890c3166175fe68cf43f12 ]

ISA v3.1 removes transactional memory and hence it should not be present
in cpu_features or cpu_user_features2. Remove CPU_FTR_TM_COMP from
CPU_FTRS_POWER10. Remove PPC_FEATURE2_HTM_COMP and
PPC_FEATURE2_HTM_NOSC_COMP from COMMON_USER2_POWER10.

Fixes: a3ea40d5c736 ("powerpc: Add POWER10 architected mode")
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200827035529.900-1-jniethe5@gmail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/powerpc/include/asm/cputable.h
arch/powerpc/kernel/cputable.c

index 32a15dc49e8ca95ba096b63bf4945ca1b93633de..ade681c1d4095af26a1f01445aa07007f8d57a91 100644 (file)
@@ -483,7 +483,7 @@ static inline void cpu_feature_keys_init(void) { }
            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
            CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
            CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
-           CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
+           CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
            CPU_FTR_DAWR | CPU_FTR_DAWR1)
 #define CPU_FTRS_CELL  (CPU_FTR_LWSYNC | \
            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
index 2aa89c6b289679a501737b4569449d167c3eed5b..0d704f1e07739863d5f08fbc2861ec762b491087 100644 (file)
@@ -120,9 +120,16 @@ extern void __restore_cpu_e6500(void);
                                 PPC_FEATURE2_DARN | \
                                 PPC_FEATURE2_SCV)
 #define COMMON_USER_POWER10    COMMON_USER_POWER9
-#define COMMON_USER2_POWER10   (COMMON_USER2_POWER9 | \
-                                PPC_FEATURE2_ARCH_3_1 | \
-                                PPC_FEATURE2_MMA)
+#define COMMON_USER2_POWER10   (PPC_FEATURE2_ARCH_3_1 | \
+                                PPC_FEATURE2_MMA | \
+                                PPC_FEATURE2_ARCH_3_00 | \
+                                PPC_FEATURE2_HAS_IEEE128 | \
+                                PPC_FEATURE2_DARN | \
+                                PPC_FEATURE2_SCV | \
+                                PPC_FEATURE2_ARCH_2_07 | \
+                                PPC_FEATURE2_DSCR | \
+                                PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \
+                                PPC_FEATURE2_VEC_CRYPTO)
 
 #ifdef CONFIG_PPC_BOOK3E_64
 #define COMMON_USER_BOOKE      (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)