u32 word;
 
        rt2x00_desc_read(priv_rx->desc, 2, &word);
-       rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->queue->data_size);
+       rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
+                          entry->queue->data_size);
        rt2x00_desc_write(priv_rx->desc, 2, word);
 
        rt2x00_desc_read(priv_rx->desc, 1, &word);
-       rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
+       rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
        rt2x00_desc_write(priv_rx->desc, 1, word);
 
        rt2x00_desc_read(priv_rx->desc, 0, &word);
        u32 word;
 
        rt2x00_desc_read(priv_tx->desc, 1, &word);
-       rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
+       rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
        rt2x00_desc_write(priv_tx->desc, 1, word);
 
        rt2x00_desc_read(priv_tx->desc, 2, &word);
 
        priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
-       rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 
        priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
-       rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 
        priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
-       rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 
        priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
-       rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 
        rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
 
        priv_rx = rt2x00dev->rx->entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
-       rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 
        return 0;
 
        u32 word;
 
        rt2x00_desc_read(priv_rx->desc, 1, &word);
-       rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
+       rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
        rt2x00_desc_write(priv_rx->desc, 1, word);
 
        rt2x00_desc_read(priv_rx->desc, 0, &word);
        u32 word;
 
        rt2x00_desc_read(priv_tx->desc, 1, &word);
-       rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
+       rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
        rt2x00_desc_write(priv_tx->desc, 1, word);
 
        rt2x00_desc_read(priv_tx->desc, 0, &word);
 
        priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
-       rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 
        priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
-       rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 
        priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
-       rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 
        priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
-       rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 
        rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
 
        priv_rx = rt2x00dev->rx->entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
-       rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 
        return 0;
 
        struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
        struct queue_entry_priv_pci_rx *priv_rx;
        struct queue_entry_priv_pci_tx *priv_tx;
-       void *desc;
+       void *addr;
+       dma_addr_t dma;
+       void *desc_addr;
+       dma_addr_t desc_dma;
        void *data_addr;
-       void *data;
        dma_addr_t data_dma;
-       dma_addr_t dma;
        unsigned int i;
 
        /*
         * Allocate DMA memory for descriptor and buffer.
         */
-       data_addr = pci_alloc_consistent(pci_dev, dma_size(queue), &data_dma);
-       if (!data_addr)
+       addr = pci_alloc_consistent(pci_dev, dma_size(queue), &dma);
+       if (!addr)
                return -ENOMEM;
 
-       memset(data_addr, 0, dma_size(queue));
+       memset(addr, 0, dma_size(queue));
 
        /*
         * Initialize all queue entries to contain valid addresses.
         */
        for (i = 0; i < queue->limit; i++) {
-               desc = desc_offset(queue, data_addr, i);
-               data = data_offset(queue, data_addr, i);
-               dma = data_offset(queue, data_dma, i);
+               desc_addr = desc_offset(queue, addr, i);
+               desc_dma = desc_offset(queue, dma, i);
+               data_addr = data_offset(queue, addr, i);
+               data_dma = data_offset(queue, dma, i);
 
                if (queue->qid == QID_RX) {
                        priv_rx = queue->entries[i].priv_data;
-                       priv_rx->desc = desc;
-                       priv_rx->data = data;
-                       priv_rx->dma = dma;
+                       priv_rx->desc = desc_addr;
+                       priv_rx->desc_dma = desc_dma;
+                       priv_rx->data = data_addr;
+                       priv_rx->data_dma = data_dma;
                } else {
                        priv_tx = queue->entries[i].priv_data;
-                       priv_tx->desc = desc;
-                       priv_tx->data = data;
-                       priv_tx->dma = dma;
+                       priv_tx->desc = desc_addr;
+                       priv_tx->desc_dma = desc_dma;
+                       priv_tx->data = data_addr;
+                       priv_tx->data_dma = data_dma;
                }
        }
 
        if (queue->qid == QID_RX) {
                priv_rx = queue->entries[0].priv_data;
                data_addr = priv_rx->data;
-               data_dma = priv_rx->dma;
+               data_dma = priv_rx->data_dma;
 
                priv_rx->data = NULL;
        } else {
                priv_tx = queue->entries[0].priv_data;
                data_addr = priv_tx->data;
-               data_dma = priv_tx->dma;
+               data_dma = priv_tx->data_dma;
 
                priv_tx->data = NULL;
        }
 
  */
 struct queue_entry_priv_pci_rx {
        __le32 *desc;
+       dma_addr_t desc_dma;
 
        void *data;
-       dma_addr_t dma;
+       dma_addr_t data_dma;
 };
 
 /**
  */
 struct queue_entry_priv_pci_tx {
        __le32 *desc;
+       dma_addr_t desc_dma;
 
        void *data;
-       dma_addr_t dma;
+       dma_addr_t data_dma;
 
        struct ieee80211_tx_control control;
 };
 
        u32 word;
 
        rt2x00_desc_read(priv_rx->desc, 5, &word);
-       rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, priv_rx->dma);
+       rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
+                          priv_rx->data_dma);
        rt2x00_desc_write(priv_rx->desc, 5, word);
 
        rt2x00_desc_read(priv_rx->desc, 0, &word);
        rt2x00_desc_write(priv_tx->desc, 5, word);
 
        rt2x00_desc_read(priv_tx->desc, 6, &word);
-       rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, priv_tx->dma);
+       rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
+                          priv_tx->data_dma);
        rt2x00_desc_write(priv_tx->desc, 6, word);
 
        rt2x00_desc_read(priv_tx->desc, 0, &word);
 
        priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
-       rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
 
        priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
-       rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
 
        priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
-       rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
 
        priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
-       rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, priv_tx->dma);
+       rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
+                          priv_tx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
 
        rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
 
        priv_rx = rt2x00dev->rx->entries[0].priv_data;
        rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
-       rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, priv_rx->dma);
+       rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
+                          priv_rx->desc_dma);
        rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
 
        rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);