enum intercept_words {
        INTERCEPT_CR = 0,
+       INTERCEPT_DR,
        MAX_INTERCEPT,
 };
 
        INTERCEPT_CR3_WRITE = 16 + 3,
        INTERCEPT_CR4_WRITE = 16 + 4,
        INTERCEPT_CR8_WRITE = 16 + 8,
+       /* Byte offset 004h (word 1) */
+       INTERCEPT_DR0_READ = 32,
+       INTERCEPT_DR1_READ,
+       INTERCEPT_DR2_READ,
+       INTERCEPT_DR3_READ,
+       INTERCEPT_DR4_READ,
+       INTERCEPT_DR5_READ,
+       INTERCEPT_DR6_READ,
+       INTERCEPT_DR7_READ,
+       INTERCEPT_DR0_WRITE = 48,
+       INTERCEPT_DR1_WRITE,
+       INTERCEPT_DR2_WRITE,
+       INTERCEPT_DR3_WRITE,
+       INTERCEPT_DR4_WRITE,
+       INTERCEPT_DR5_WRITE,
+       INTERCEPT_DR6_WRITE,
+       INTERCEPT_DR7_WRITE,
 };
 
 enum {
 
 struct __attribute__ ((__packed__)) vmcb_control_area {
        u32 intercepts[MAX_INTERCEPT];
-       u32 intercept_dr;
        u32 intercept_exceptions;
        u64 intercept;
        u8 reserved_1[40];
 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
 #define SVM_SELECTOR_CODE_MASK (1 << 3)
 
-#define INTERCEPT_DR0_READ     0
-#define INTERCEPT_DR1_READ     1
-#define INTERCEPT_DR2_READ     2
-#define INTERCEPT_DR3_READ     3
-#define INTERCEPT_DR4_READ     4
-#define INTERCEPT_DR5_READ     5
-#define INTERCEPT_DR6_READ     6
-#define INTERCEPT_DR7_READ     7
-#define INTERCEPT_DR0_WRITE    (16 + 0)
-#define INTERCEPT_DR1_WRITE    (16 + 1)
-#define INTERCEPT_DR2_WRITE    (16 + 2)
-#define INTERCEPT_DR3_WRITE    (16 + 3)
-#define INTERCEPT_DR4_WRITE    (16 + 4)
-#define INTERCEPT_DR5_WRITE    (16 + 5)
-#define INTERCEPT_DR6_WRITE    (16 + 6)
-#define INTERCEPT_DR7_WRITE    (16 + 7)
-
 #define SVM_EVTINJ_VEC_MASK 0xff
 
 #define SVM_EVTINJ_TYPE_SHIFT 8
 
        for (i = 0; i < MAX_INTERCEPT; i++)
                c->intercepts[i] = h->intercepts[i];
 
-       c->intercept_dr = h->intercept_dr;
        c->intercept_exceptions = h->intercept_exceptions;
        c->intercept = h->intercept;
 
        for (i = 0; i < MAX_INTERCEPT; i++)
                c->intercepts[i] |= g->intercepts[i];
 
-       c->intercept_dr |= g->intercept_dr;
        c->intercept_exceptions |= g->intercept_exceptions;
        c->intercept |= g->intercept;
 }
        for (i = 0; i < MAX_INTERCEPT; i++)
                dst->intercepts[i] = from->intercepts[i];
 
-       dst->intercept_dr         = from->intercept_dr;
        dst->intercept_exceptions = from->intercept_exceptions;
        dst->intercept            = from->intercept;
        dst->iopm_base_pa         = from->iopm_base_pa;
                break;
        }
        case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
-               u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
-               if (svm->nested.ctl.intercept_dr & bit)
+               if (vmcb_is_intercept(&svm->nested.ctl, exit_code))
                        vmexit = NESTED_EXIT_DONE;
                break;
        }
 
        pr_err("VMCB Control Area:\n");
        pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
        pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
-       pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
-       pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
+       pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
+       pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
        pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
        pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
        pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
 
 {
        struct vmcb *vmcb = get_host_vmcb(svm);
 
-       vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
-               | (1 << INTERCEPT_DR1_READ)
-               | (1 << INTERCEPT_DR2_READ)
-               | (1 << INTERCEPT_DR3_READ)
-               | (1 << INTERCEPT_DR4_READ)
-               | (1 << INTERCEPT_DR5_READ)
-               | (1 << INTERCEPT_DR6_READ)
-               | (1 << INTERCEPT_DR7_READ)
-               | (1 << INTERCEPT_DR0_WRITE)
-               | (1 << INTERCEPT_DR1_WRITE)
-               | (1 << INTERCEPT_DR2_WRITE)
-               | (1 << INTERCEPT_DR3_WRITE)
-               | (1 << INTERCEPT_DR4_WRITE)
-               | (1 << INTERCEPT_DR5_WRITE)
-               | (1 << INTERCEPT_DR6_WRITE)
-               | (1 << INTERCEPT_DR7_WRITE);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
+       vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
 
        recalc_intercepts(svm);
 }
 {
        struct vmcb *vmcb = get_host_vmcb(svm);
 
-       vmcb->control.intercept_dr = 0;
+       vmcb->control.intercepts[INTERCEPT_DR] = 0;
 
        recalc_intercepts(svm);
 }