ARM: entry: no need to reload the SPSR value from struct pt_regs

The SVC IRQ, prefetch and data abort handlers preserve the SPSR value
via r5 across the exception.  Rather than re-loading it from pt_regs,
use the preserved value instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bbdd443b80556d5d5f627c49b8a0329e3e14e2f8..fa02a22a4c4b5868959a66adc6e94003f3e489f9 100644 (file)
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -195,10 +195,6 @@ __dabt_svc:
        @
        disable_irq_notrace
 
-       @
-       @ restore SPSR and restart the instruction
-       @
-       ldr     r5, [sp, #S_PSR]
 #ifdef CONFIG_TRACE_IRQFLAGS
        tst     r5, #PSR_I_BIT
        bleq    trace_hardirqs_on
@@ -223,7 +219,7 @@ __irq_svc:
        tst     r0, #_TIF_NEED_RESCHED
        blne    svc_preempt
 #endif
-       ldr     r5, [sp, #S_PSR]
+
 #ifdef CONFIG_TRACE_IRQFLAGS
        @ The parent context IRQs must have been enabled to get here in
        @ the first place, so there's no point checking the PSR I bit.
@@ -308,10 +304,6 @@ __pabt_svc:
        @
        disable_irq_notrace
 
-       @
-       @ restore SPSR and restart the instruction
-       @
-       ldr     r5, [sp, #S_PSR]
 #ifdef CONFIG_TRACE_IRQFLAGS
        tst     r5, #PSR_I_BIT
        bleq    trace_hardirqs_on