arm64: dts: imx: add imx8qm mek support

The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53
proccessor with powerful graphic and multimedia features.
This patch adds i.MX8QuadMax MEK board support.

Note that MX8QM needs a special workaround for TLB flush due to a SoC
errata, otherwise there may be random crash if enable both clusters of
A72 and A53. As the errata workaround is still not in mainline, so we
disable A72 cluster first for MX8QM MEK.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index ecdcf9de693febaa83f26ecfc54d4a44a4f2d01f..44890d56c194d295410d77b6b5c4ac7866674aed 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
new file mode 100644 (file)
index 0000000..ce9d3f0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ *     Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+/dts-v1/;
+
+#include "imx8qm.dtsi"
+
+/ {
+       model = "Freescale i.MX8QM MEK";
+       compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+       chosen {
+               stdout-path = &lpuart0;
+       };
+
+       cpus {
+               /delete-node/ cpu-map;
+               /delete-node/ cpu@100;
+               /delete-node/ cpu@101;
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x00000000 0x80000000 0 0x40000000>;
+       };
+
+       reg_usdhc2_vmmc: usdhc2-vmmc {
+               compatible = "regulator-fixed";
+               regulator-name = "SD1_SPWR";
+               regulator-min-microvolt = <3000000>;
+               regulator-max-microvolt = <3000000>;
+               gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+};
+
+&lpuart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpuart0>;
+       status = "okay";
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+               };
+
+               ethphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+               };
+       };
+};
+
+&usdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       bus-width = <8>;
+       no-sd;
+       no-sdio;
+       non-removable;
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       bus-width = <4>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       IMX8QM_ENET0_MDC_CONN_ENET0_MDC                         0x06000020
+                       IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO                       0x06000020
+                       IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL       0x06000020
+                       IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC             0x06000020
+                       IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0           0x06000020
+                       IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1           0x06000020
+                       IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2           0x06000020
+                       IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3           0x06000020
+                       IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC             0x06000020
+                       IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL       0x06000020
+                       IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0           0x06000020
+                       IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1           0x06000020
+                       IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2           0x06000020
+                       IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3           0x06000020
+               >;
+       };
+
+       pinctrl_lpuart0: lpuart0grp {
+               fsl,pins = <
+                       IMX8QM_UART0_RX_DMA_UART0_RX                            0x06000020
+                       IMX8QM_UART0_TX_DMA_UART0_TX                            0x06000020
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK                         0x06000041
+                       IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD                         0x00000021
+                       IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0                     0x00000021
+                       IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1                     0x00000021
+                       IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2                     0x00000021
+                       IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3                     0x00000021
+                       IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4                     0x00000021
+                       IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5                     0x00000021
+                       IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6                     0x00000021
+                       IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7                     0x00000021
+                       IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE                   0x00000041
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK                       0x06000041
+                       IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD                       0x00000021
+                       IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0                   0x00000021
+                       IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1                   0x00000021
+                       IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2                   0x00000021
+                       IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3                   0x00000021
+                       IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT               0x00000021
+               >;
+       };
+};