]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
drm/amd/display: incorrect conditions for failing dto calculations
authorClay King <clayking@amd.com>
Wed, 20 Aug 2025 19:04:29 +0000 (15:04 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 29 Aug 2025 14:14:05 +0000 (10:14 -0400)
[Why & How]
Previously, when calculating dto phase, we would incorrectly fail when phase
<=0 without additionally checking for the integer value. This meant that
calculations would incorrectly fail when the desired pixel clock was an exact
multiple of the reference clock.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

index 668ee2d405fdf520c81f3db1c4849e0abe280b84..0b8ed9b94d3c55e1111b04c5c1cacec5480a187b 100644 (file)
@@ -619,7 +619,7 @@ void dccg401_set_dp_dto(
                dto_integer = div_u64(params->pixclk_hz, dto_modulo_hz);
                dto_phase_hz = params->pixclk_hz - dto_integer * dto_modulo_hz;
 
-               if (dto_phase_hz <= 0) {
+               if (dto_phase_hz <= 0 && dto_integer <= 0) {
                        /* negative pixel rate should never happen */
                        BREAK_TO_DEBUGGER();
                        return;