clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150

QUPv3 clocks support DFS and thus register the RCGs which require
support for the same.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240111-sm8150-dfs-support-v2-1-6edb44c83d3b@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 05d115c52dfebbb4f2d6101ba2f580031326d4f4..80315307dbb4f49362b81b161a173d3545b93cb9 100644 (file)
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -453,19 +453,29 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
        { }
 };
 
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s0_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
        .cmd_rcgr = 0x17148,
        .mnd_width = 16,
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s0_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s1_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -474,13 +484,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s1_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s2_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -489,13 +501,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s2_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s3_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -504,13 +518,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s3_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s4_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -519,13 +535,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s4_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s5_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -534,13 +552,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s5_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s6_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -549,13 +569,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s6_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s7_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -564,13 +586,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s7_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s0_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -579,13 +603,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s0_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s1_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -594,13 +620,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s1_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s2_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -609,13 +637,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s2_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s3_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -624,13 +654,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s3_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s4_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -639,13 +671,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s4_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s5_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -654,13 +688,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s5_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s0_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@@ -669,13 +705,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap2_s0_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s1_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@@ -684,13 +722,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap2_s1_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s2_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
@@ -699,13 +739,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap2_s2_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s3_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@@ -714,13 +756,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap2_s3_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s4_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@@ -729,13 +773,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap2_s4_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s5_clk_src",
+       .parent_data = gcc_parents_0,
+       .num_parents = ARRAY_SIZE(gcc_parents_0),
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@@ -744,13 +790,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap2_s5_clk_src",
-               .parent_data = gcc_parents_0,
-               .num_parents = ARRAY_SIZE(gcc_parents_0),
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_rcg2_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
 };
 
 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
@@ -3750,6 +3790,29 @@ static struct gdsc *gcc_sm8150_gdscs[] = {
        [USB30_SEC_GDSC] = &usb30_sec_gdsc,
 };
 
+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
+};
+
 static const struct regmap_config gcc_sm8150_regmap_config = {
        .reg_bits       = 32,
        .reg_stride     = 4,
@@ -3777,6 +3840,7 @@ MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
 static int gcc_sm8150_probe(struct platform_device *pdev)
 {
        struct regmap *regmap;
+       int ret;
 
        regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
        if (IS_ERR(regmap))
@@ -3786,6 +3850,11 @@ static int gcc_sm8150_probe(struct platform_device *pdev)
        regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
        regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
 
+       ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
+                                      ARRAY_SIZE(gcc_dfs_clocks));
+       if (ret)
+               dev_err_probe(&pdev->dev, ret, "Failed to register with DFS!\n");
+
        return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
 }