clk: renesas: r9a07g043: Add MTU3a clock and reset entry

Add MTU3a clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230714075649.146978-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 99f72bf590fa0a6f6bfe5c4380846ccde93204a9..1a7a6d60aca44b546370c2a2e722aa9a7c1f1c11 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -154,6 +154,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
                                0x534, 1),
        DEF_MOD("ostm2_pclk",   R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
                                0x534, 2),
+       DEF_MOD("mtu_x_mck",    R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0,
+                               0x538, 0),
        DEF_MOD("wdt0_pclk",    R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
                                0x548, 0),
        DEF_MOD("wdt0_clk",     R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
@@ -264,6 +266,7 @@ static struct rzg2l_reset r9a07g043_resets[] = {
        DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
        DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
        DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
+       DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),
        DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
        DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
        DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),