iommu/arm-smmu-v3: Add feature detection for HTTU

If the SMMU supports it and the kernel was built with HTTU support,
Probe support for Hardware Translation Table Update (HTTU) which is
essentially to enable hardware update of access and dirty flags.

Probe and set the smmu::features for Hardware Dirty and Hardware Access
bits. This is in preparation, to enable it on the context descriptors of
stage 1 format.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Ryan Roberts <ryan.roberts@arm.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Link: https://lore.kernel.org/r/20240703101604.2576-3-shameerali.kolothum.thodi@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index c616a38ecf28128b9a88273c6d09d3f683309d30..6b35954940b81bd9e9f038a70e3bebd88a94b89e 100644 (file)
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -4014,6 +4014,28 @@ static void arm_smmu_device_iidr_probe(struct arm_smmu_device *smmu)
        }
 }
 
+static void arm_smmu_get_httu(struct arm_smmu_device *smmu, u32 reg)
+{
+       u32 fw_features = smmu->features & (ARM_SMMU_FEAT_HA | ARM_SMMU_FEAT_HD);
+       u32 hw_features = 0;
+
+       switch (FIELD_GET(IDR0_HTTU, reg)) {
+       case IDR0_HTTU_ACCESS_DIRTY:
+               hw_features |= ARM_SMMU_FEAT_HD;
+               fallthrough;
+       case IDR0_HTTU_ACCESS:
+               hw_features |= ARM_SMMU_FEAT_HA;
+       }
+
+       if (smmu->dev->of_node)
+               smmu->features |= hw_features;
+       else if (hw_features != fw_features)
+               /* ACPI IORT sets the HTTU bits */
+               dev_warn(smmu->dev,
+                        "IDR0.HTTU features(0x%x) overridden by FW configuration (0x%x)\n",
+                         hw_features, fw_features);
+}
+
 static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
 {
        u32 reg;
@@ -4074,6 +4096,8 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
                        smmu->features |= ARM_SMMU_FEAT_E2H;
        }
 
+       arm_smmu_get_httu(smmu, reg);
+
        /*
         * The coherency feature as set by FW is used in preference to the ID
         * register, but warn on mismatch.
@@ -4269,6 +4293,14 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
        if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE)
                smmu->features |= ARM_SMMU_FEAT_COHERENCY;
 
+       switch (FIELD_GET(ACPI_IORT_SMMU_V3_HTTU_OVERRIDE, iort_smmu->flags)) {
+       case IDR0_HTTU_ACCESS_DIRTY:
+               smmu->features |= ARM_SMMU_FEAT_HD;
+               fallthrough;
+       case IDR0_HTTU_ACCESS:
+               smmu->features |= ARM_SMMU_FEAT_HA;
+       }
+
        return 0;
 }
 #else

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index a05e02d6afd1db56321b2dbe99f5b0c612b7de38..af74b59032b550b4636431a9517dccefb9591d7b 100644 (file)
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -33,6 +33,9 @@
 #define IDR0_ASID16                    (1 << 12)
 #define IDR0_ATS                       (1 << 10)
 #define IDR0_HYP                       (1 << 9)
+#define IDR0_HTTU                      GENMASK(7, 6)
+#define IDR0_HTTU_ACCESS               1
+#define IDR0_HTTU_ACCESS_DIRTY         2
 #define IDR0_COHACC                    (1 << 4)
 #define IDR0_TTF                       GENMASK(3, 2)
 #define IDR0_TTF_AARCH64               2
@@ -650,6 +653,8 @@ struct arm_smmu_device {
 #define ARM_SMMU_FEAT_E2H              (1 << 18)
 #define ARM_SMMU_FEAT_NESTING          (1 << 19)
 #define ARM_SMMU_FEAT_ATTR_TYPES_OVR   (1 << 20)
+#define ARM_SMMU_FEAT_HA               (1 << 21)
+#define ARM_SMMU_FEAT_HD               (1 << 22)
        u32                             features;
 
 #define ARM_SMMU_OPT_SKIP_PREFETCH     (1 << 0)