drm/msm/dpu: fix the programming of INTF_CFG2_DATA_HCTL_EN

Currently INTF_CFG2_DATA_HCTL_EN is coupled with the enablement
of widebus but this is incorrect because we should be enabling
this bit independent of widebus except for cases where compression
is enabled in one pixel per clock mode.

Fix this by making the condition checks more explicit and enabling
INTF_CFG2_DATA_HCTL_EN for all other cases when supported by DPU.

Fixes: 3309a7563971 ("drm/msm/dpu: revise timing engine programming to support widebus feature")
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/576722/
Link: https://lore.kernel.org/r/20240201004737.2478-1-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 6a4b489d44e5173831d73956f1fb7a4e10809052..8932f38a41b2da311b92b6e876db0da960140a2a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -226,6 +226,13 @@ bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
        return dpu_enc->wide_bus_en;
 }
 
+bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc)
+{
+       const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+       return dpu_enc->dsc ? true : false;
+}
+
 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
 {
        struct dpu_encoder_virt *dpu_enc;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 4c05fd5e9ed18df7fd556862c79c2c4faf528f50..fe6b1d312a742e5d7f8a26b3e2cb75c26364df77 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -158,6 +158,13 @@ int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
 
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc);
 
+/**
+ * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
+ *                             for the encoder.
+ * @drm_enc:    Pointer to previously created drm encoder structure
+ */
+bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc);
+
 /**
  * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
  *     in virtual encoder that can collect CRC values

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d0f56c5c4cce9691dd18c21a4e35f2d1236adfb0..f562beb6f797179773835788406006c5770e3c24 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -102,6 +102,7 @@ static void drm_mode_to_intf_timing_params(
        }
 
        timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
+       timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
 
        /*
         * for DP, divide the horizonal parameters by 2 when

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 6bba531d6dc41e3a3cbaeabc592284334ade8e4d..965692ef7892c64e52a79626270e4768696207f9 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -163,13 +163,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
        hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
        display_hctl = (hsync_end_x << 16) | hsync_start_x;
 
-       /*
-        * DATA_HCTL_EN controls data timing which can be different from
-        * video timing. It is recommended to enable it for all cases, except
-        * if compression is enabled in 1 pixel per clock mode
-        */
        if (p->wide_bus_en)
-               intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN;
+               intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
 
        data_width = p->width;
 
@@ -229,6 +224,14 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
        DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
        DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
        if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) {
+               /*
+                * DATA_HCTL_EN controls data timing which can be different from
+                * video timing. It is recommended to enable it for all cases, except
+                * if compression is enabled in 1 pixel per clock mode
+                */
+               if (!(p->compression_en && !p->wide_bus_en))
+                       intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN;
+
                DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
                DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);
                DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 0bd57a32144a610cc3ba48514e50ca23236c5ef4..6f4c87244f944cecb5da0ababff73c7ab7038579 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -33,6 +33,7 @@ struct dpu_hw_intf_timing_params {
        u32 hsync_skew;
 
        bool wide_bus_en;
+       bool compression_en;
 };
 
 struct dpu_hw_intf_prog_fetch {