drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8
bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
receiver capabilities. For panels that use this new feature wait interval
would be increased by 512 ms, when spec is max 16 ms. This behavior is
described in table 2-158 of DP 1.4 spec address 0000eh.

With the introduction of DP 1.4 spec main link clock recovery was
standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value.

To avoid breaking panels that are not spec compiant we now warn on
invalid values.

V2: commit title/message, masking all 7 bits, warn on out of spec values.
V3: commit message, make link train clock recovery follow DP 1.4 spec.
V4: style changes
V5: typo
V6: print statement revisions, DP_REV to DPCD_REV, comment correction
V7: typo
V8: Style
V9: Strip out DPCD_REV_XX into seperate patch
v10: DPCD_REV_XX to DP_DPCD_REV_XX

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180504221800.17830-2-matthew.s.atwood@intel.com

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ffe14ec3e7f274d9099aeed6b7e29bf04b043325..36c7609a4bd5fd3448e68f4c681a90c48c7d83d4 100644 (file)
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -119,18 +119,32 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
-       if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+       int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+                         DP_TRAINING_AUX_RD_MASK;
+
+       if (rd_interval > 4)
+               DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
+                             rd_interval);
+
+       if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
                udelay(100);
        else
-               mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+               mdelay(rd_interval * 4);
 }
 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
 
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
-       if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+       int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+                         DP_TRAINING_AUX_RD_MASK;
+
+       if (rd_interval > 4)
+               DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
+                             rd_interval);
+
+       if (rd_interval == 0)
                udelay(400);
        else
-               mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+               mdelay(rd_interval * 4);
 }
 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
 

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index fc01341a46fa748d79a4673f85b3048674b21195..c7b285637f86298b4aba831a548d3ef509e53661 100644 (file)
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -124,6 +124,7 @@
 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
 
 #define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
+# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
 
 #define DP_ADAPTER_CAP                     0x00f   /* 1.2 */
 # define DP_FORCE_LOAD_SENSE_CAP           (1 << 0)