Modifications since 0.7.0:
======================================================================
+* Added support for PPC405CR (Stefan Roese)
+
+* Fixes in environment code; better detection of CRC errors
+
+* Fixed serial driver over SCC; for MPC8xx now tested on all 4 SCC's
+
* For IP860, set SRAM information in bd_info
* Fix FADS860T configuration
echo "CPU = ppc4xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+AR405_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = ar405" >>config.mk ; \
+ echo "CPU = ppc4xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
+CANBT_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = canbt" >>config.mk ; \
+ echo "CPU = ppc4xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
ADCIOP_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
+SOBJS = init.o
-$(LIB): $(OBJS)
+$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
#include <ppcboot.h>
#include "cpci405.h"
+#include <asm/processor.h>
+
/* ------------------------------------------------------------------------- */
-#define _NOT_USED_ 0xFFFFFFFF
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */
+
+#define IBM405GP_GPIO0_OR 0xef600700 /* GPIO Output */
+#define IBM405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
+#define IBM405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
+#define IBM405GP_GPIO0_IR 0xef60071c /* GPIO Input */
+
+/* fpga configuration data - generated by bit2inc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+
+/******************************************************************************
+ *
+ * fpga_boot - Load fpga-image into fpga
+ *
+ */
+static int fpga_boot(void)
+{
+ int i,j,index,len;
+ unsigned char b;
+ int size = sizeof(fpgadata);
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++)
+ {
+ len = fpgadata[index];
+#ifdef FPGA_DEBUG
+ printf("FPGA: %s\n", &(fpgadata[index+1]));
+#endif
+ index += len+3;
+ }
+
+ /* search for preamble 0xFF2X */
+ for (index = 0; index < size-1 ; index++)
+ {
+ if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x20))
+ break;
+ }
+#ifdef FPGA_DEBUG
+ printf("FPGA: configdata starts at position 0x%x\n",index);
+ printf("FPGA: length of fpga-data %d\n", size-index);
+#endif
+
+ /*
+ * Setup port pins for fpga programming
+ */
+ out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32(IBM405GP_GPIO0_TCR, 0x07000000); /* setup for output */
+ out32(IBM405GP_GPIO0_OR, 0x07000000); /* set output pins to high (default) */
+
+#ifdef FPGA_DEBUG
+ printf("%s\n",((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0) ? "NOT DONE" : "DONE" );
+#endif
+
+ /*
+ * Init fpga by asserting and deasserting PROGRAM*
+ */
+ out32(IBM405GP_GPIO0_OR, 0x03000000);
+ udelay(FPGA_PRG_SLEEP*1000);
+#ifdef FPGA_DEBUG
+ printf("%s\n",((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0) ? "NOT DONE" : "DONE" );
+#endif
+ out32(IBM405GP_GPIO0_OR, 0x07000000);
+ udelay(FPGA_PRG_SLEEP*1000);
+#ifdef FPGA_DEBUG
+ printf("%s\n",((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0) ? "NOT DONE" : "DONE" );
+#endif
+
+ /* write configuration-data into fpga... */
+ for (i=index; i<size; i++)
+ {
+ b = fpgadata[i];
+ for (j=0; j<8; j++)
+ {
+ if ((b & 0x80) == 0x80)
+ {
+ /*
+ * Write 1 to fpga
+ */
+ out32(IBM405GP_GPIO0_OR, 0x05000000); /* set clock to 0 */
+ out32(IBM405GP_GPIO0_OR, 0x05000000); /* set data to 1 */
+ out32(IBM405GP_GPIO0_OR, 0x07000000); /* set clock to 1 */
+ out32(IBM405GP_GPIO0_OR, 0x07000000); /* set data to 1 */
+ }
+ else
+ {
+ /*
+ * Write 0 to fpga
+ */
+ out32(IBM405GP_GPIO0_OR, 0x05000000); /* set clock to 0 */
+ out32(IBM405GP_GPIO0_OR, 0x04000000); /* set data to 0 */
+ out32(IBM405GP_GPIO0_OR, 0x06000000); /* set clock to 1 */
+ out32(IBM405GP_GPIO0_OR, 0x07000000); /* set data to 1 */
+ }
+
+ /*
+ * Shift to next bit
+ */
+ b <<= 1;
+ }
+ }
+
+ udelay(FPGA_PRG_SLEEP*1000);
+#ifdef FPGA_DEBUG
+ printf("%s\n",((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0) ? "NOT DONE" : "DONE" );
+#endif
+
+ /*
+ * Check if fpga's DONE signal - correctly booted ?
+ */
+ if ((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0)
+ {
+#ifdef FPGA_DEBUG
+ printf("FPGA: Booting failed!\n");
+#endif
+ return -1;
+ }
+ else
+ {
+#ifdef FPGA_DEBUG
+ printf("FPGA: Booting successful!\n");
+#endif
+ return 0;
+ }
+}
+
+
+int board_pre_init (void)
+{
+ /*
+ * Boot onboard FPGA
+ */
+ while (fpga_boot() != 0);
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
- *
- * Test TQ ID string (TQM8xx...)
- * If present, check for "L" type (no second DRAM bank),
- * otherwise "L" type is assumed as default.
- *
- * Return 1 for "L" type, 0 else.
*/
int checkboard (void)
{
unsigned char *s = getenv("serial#");
unsigned char *e;
- int l_type;
-
- if (!s || strncmp(s, "CPCI405", 7)) {
- printf ("### No HW ID - assuming CPCI405\n");
- return (1);
- }
+ int i;
+ int index;
+ int len;
- l_type = (*(s+6) == 'L');
-
- for (e=s; *e; ++e) {
- if (*e == ' ')
+ if (!s || strncmp(s, "CPCI405", 7))
+ {
+ printf ("### No HW ID - assuming CPCI405");
+ }
+ else
+ {
+ for (e=s; *e; ++e) {
+ if (*e == ' ')
break;
- }
+ }
- for ( ; s<e; ++s) {
- putc (*s);
- }
+ for ( ; s<e; ++s) {
+ putc (*s);
+ }
+ }
+
+ printf("\n FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++)
+ {
+ len = fpgadata[index];
+ printf("%s ", &(fpgadata[index+1]));
+ index += len+3;
+ }
+
putc ('\n');
- return (l_type);
+ return (0);
}
/* ------------------------------------------------------------------------- */
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
ulong start, now, last;
+ int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type - aborted\n");
return;
}
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- udelay(50000); /* wait 50 ms */
+ for (i=0; i<50; i++)
+ udelay(1000); /* wait 1 ms */
} else {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
--- /dev/null
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+ 0x63,0x70,0x63,0x69,0x34,0x30,0x35,0x32,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+ 0x73,0x30,0x35,0x78,0x6c,0x76,0x71,0x31,0x30,0x30,0x00,0x63,0x00,0x0b,0x32,0x30,
+ 0x30,0x30,0x2f,0x31,0x31,0x2f,0x32,0x39,0x00,0x64,0x00,0x09,0x31,0x34,0x3a,0x35,
+ 0x37,0x3a,0x33,0x32,0x00,0x65,0x00,0x00,0x1a,0xa2,0xff,0x20,0x0d,0x50,0x9f,0x5b,
+ 0xff,0xee,0xfb,0xbe,0xef,0xfb,0xee,0xf7,0xbd,0xfb,0x7b,0xde,0xff,0xef,0xfa,0xff,
+ 0xfb,0xbe,0xef,0xbf,0xee,0xfb,0xbf,0xfb,0xfe,0xff,0xef,0xdb,0xbb,0xff,0xf9,0xff,
+ 0xff,0x7f,0xff,0xf7,0xfc,0xff,0xff,0xfb,0xff,0xff,0x3f,0xcf,0xfb,0xff,0xeb,0xff,
+ 0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xff,0xbf,0xef,0xfb,0x3e,0x8f,0xbf,0xff,0xd7,0xff,
+ 0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbe,0xf9,0xbe,0xef,0x9b,0xe7,0xfb,0xff,0x6f,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x37,0xcf,0xff,0xfe,0x97,0xbf,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xdf,0xff,0xfb,0xbf,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xfc,0xdf,0x7f,0xff,0xfd,0x5e,0xff,
+ 0xfe,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xdf,0xff,0xff,0xbf,0xfe,0xe4,0xbd,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,0xff,0xc9,0x7f,0xfb,
+ 0xff,0xff,0xff,0xef,0xf3,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0x83,0xfd,0xff,
+ 0xff,0xff,0xff,0xff,0xef,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd7,0xfb,0xff,
+ 0xdf,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0x6f,0x7f,0xf7,
+ 0xbd,0xff,0x7f,0xdf,0xf7,0xff,0x7f,0xdf,0xf7,0xfd,0xef,0x7f,0xfe,0x1f,0xff,0xef,
+ 0xfb,0xfe,0xff,0xbf,0xef,0xee,0xff,0xbf,0xef,0xfb,0xfe,0x7f,0xf8,0xbf,0xfe,0x7f,
+ 0x9f,0xa7,0xd9,0xfe,0x7f,0xc7,0xf9,0xfe,0x7e,0x9f,0xe7,0xff,0xf3,0x7f,0xff,0xbf,
+ 0xef,0xfb,0xfe,0xff,0xbd,0x73,0xfc,0xff,0x3f,0xc7,0xfb,0xff,0xfc,0xfd,0xf9,0xfe,
+ 0x7f,0x9f,0xe7,0xf9,0xff,0x97,0xe7,0xf9,0x7e,0x7f,0x9f,0xed,0xcd,0xff,0xfd,0xff,
+ 0x7f,0xdf,0xf7,0xfd,0xff,0xf7,0xff,0xff,0x77,0xd9,0xdf,0xff,0xbb,0xff,0xef,0xfb,
+ 0xfe,0xff,0xbf,0xef,0xea,0xff,0xbb,0xeb,0xfa,0xfe,0xff,0xff,0x27,0xff,0xdb,0xf6,
+ 0xfd,0x9d,0x6f,0xdb,0xf5,0xbb,0x6f,0xdb,0xb6,0xe5,0xbf,0xdf,0x2e,0xff,0xfb,0xff,
+ 0xff,0xff,0xff,0xfd,0xfe,0xdf,0xff,0xfb,0xff,0xef,0xff,0xdc,0x5f,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0x79,0x3f,0xff,0xff,0xff,
+ 0xff,0xdf,0xff,0xff,0xfd,0xfe,0xd7,0xdf,0xe3,0xbf,0xff,0xf1,0x7f,0xff,0xff,0xbf,
+ 0xff,0xf3,0xf6,0xf7,0xbe,0xdf,0xff,0xff,0xfd,0xff,0xdd,0x7a,0xff,0xff,0x3f,0xdf,
+ 0xf7,0xf5,0xff,0x7f,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xff,0xd5,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0x6f,0xff,0xb6,0xe5,0xff,0xff,0x77,0x9b,0xff,0xbf,0xff,0xff,
+ 0xff,0xff,0xff,0xfe,0xfd,0xff,0x6f,0xff,0xf7,0xff,0xff,0x17,0xef,0xff,0xff,0xff,
+ 0xff,0xfb,0xfd,0xfd,0xff,0xff,0xdf,0xfb,0xff,0xff,0xfe,0x0f,0xdf,0xff,0xff,0xdf,
+ 0xff,0xff,0xf7,0xf7,0xfd,0xef,0xf7,0xdf,0xf7,0xff,0xfe,0x9f,0xff,0xfb,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xb8,0x3f,0xf7,0xff,0xff,0x7f,
+ 0xff,0xff,0xff,0xe9,0xfa,0xfe,0xbd,0xaf,0xff,0xbf,0x7a,0x7e,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfb,0xf5,0xfd,0xbf,0x9f,0xff,0xff,0xe2,0xff,0xff,0xff,0xff,0xfd,
+ 0xff,0xff,0xff,0xbf,0xff,0xf7,0xff,0xff,0x7f,0xfd,0xc1,0xff,0x7f,0x7f,0xff,0xff,
+ 0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xdb,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xfd,0xf7,0xa7,0xff,0xff,0xff,0xff,0xff,
+ 0xfe,0xff,0xff,0xdf,0xff,0xff,0xff,0x7f,0xff,0xee,0x4f,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xfe,0x1f,0xff,0xfb,0xff,0xff,0xff,
+ 0xff,0xfe,0xef,0x5f,0xff,0xff,0xff,0xff,0xfe,0xfc,0xbf,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xdf,0xff,0xf7,0xff,0xfd,0xff,0x7f,0xf2,0x7f,0xff,0xff,0xf3,0xbf,0xff,
+ 0xff,0xff,0xff,0x7f,0xef,0xff,0xff,0xff,0xff,0xec,0x3f,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe9,0xaf,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xe7,0xff,0xff,0xf7,0x8b,0xdf,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xef,0xb6,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xfe,0x4f,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xdb,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdb,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbd,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf4,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x89,0xff,0x8f,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe9,0xff,0xfb,0xfe,0xff,0xbf,0xef,0xfb,
+ 0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xfe,0xa6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xfc,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xd0,0x7f,0xff,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,
+ 0xff,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe1,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x97,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x8f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xf2,0x3f,0xfd,0xeb,0xfa,0xfe,0x97,0xaf,0xeb,0xfe,
+ 0xbf,0xad,0xeb,0xfa,0xfe,0xbb,0xf5,0x7f,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xa8,0x7f,0xff,0xfb,0xff,0xff,0xff,0xff,0xfb,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xb5,0xff,0xff,0xbf,0xf9,0xff,0xff,0xff,0xfc,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xa9,0x7f,0xff,0xbf,0xff,0xff,0xff,0xff,0xfb,0xff,
+ 0xff,0x7f,0xdf,0xff,0xf7,0xef,0xd7,0xff,0xff,0xef,0xff,0xff,0xfe,0xff,0xf7,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xfd,0x47,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xef,0xff,
+ 0xff,0xfe,0xff,0xff,0xff,0xdb,0xdf,0xff,0xff,0x7f,0xef,0xff,0xff,0xff,0xdf,0xff,
+ 0xff,0xfd,0xff,0xff,0xff,0xf5,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9f,0xff,
+ 0xff,0xff,0xff,0xff,0xef,0xf7,0x7f,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0x7f,0xff,
+ 0xff,0xfb,0xff,0xff,0xff,0xc8,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xf1,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xc3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0x25,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xfb,0xff,0xff,
+ 0xff,0xff,0xdf,0xff,0xff,0x8b,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xf4,0x5b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xf9,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfe,0x52,0x2d,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0x40,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xa9,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfd,0x19,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfe,0x63,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfd,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0x8f,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfc,0x0f,0xef,0xbf,0xef,0xfb,0xf6,0xff,0xbf,0xfb,0xfe,0xff,0xbf,
+ 0xef,0xfb,0xff,0xa4,0x6f,0xff,0xff,0xff,0xbf,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfc,0xff,0xff,0xff,0xfe,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0x59,0xff,0xff,0xff,0xff,0xdf,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0x83,0xff,0xff,0xff,0xfe,0xdf,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xa7,0xff,0xff,0xff,0xff,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xfb,0xfd,0x2f,0xff,0xfe,0xdf,0xe3,0xe8,0xfb,0x7f,0xdf,0xed,0xfe,0x7f,0x9f,
+ 0xe7,0xf9,0xfe,0xdf,0xff,0xff,0xff,0xfd,0xd7,0x77,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xf9,0x3f,0xff,0xff,0x7f,0xef,0xfb,0xfd,0xff,0x7f,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xf2,0x7f,0xff,0xf4,0xff,0xf7,0xdd,0xf3,0xfc,0xff,0x5f,0xff,0xff,0xff,
+ 0xff,0xff,0xf6,0xff,0xff,0xe7,0xff,0xbe,0xef,0x9f,0xe7,0xfe,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xdd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xbb,0xff,0xfe,0x9f,0xa7,0xeb,0xf8,0xfe,0xbf,0xea,0xfa,0xbe,0xb7,0xad,
+ 0xeb,0xfd,0xd7,0xff,0xff,0xdf,0xff,0xef,0xff,0x7f,0xff,0xfb,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xc7,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,
+ 0xff,0xf8,0x5f,0xff,0xff,0xff,0xff,0xfb,0xfa,0xf7,0xdf,0xff,0xff,0xff,0xff,0xff,
+ 0xbf,0xfe,0x9f,0xff,0xff,0xf7,0xfd,0xff,0xff,0xff,0x9f,0xff,0xf7,0xff,0xff,0xff,
+ 0xff,0xf0,0x7f,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xfb,0xff,0xff,0xfd,
+ 0xff,0xf2,0x7f,0xde,0xdf,0xff,0x7f,0xff,0xff,0xf6,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xc1,0xff,0xfb,0xdb,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xdf,0xff,0xff,0xff,
+ 0xff,0x8b,0xf7,0xff,0xdf,0xff,0xff,0xff,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,0xfe,
+ 0xff,0x97,0x7f,0xbf,0xff,0xff,0xff,0xff,0xbf,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0x2b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xfc,0xdd,0xfb,0xff,0xff,0xff,0xff,0xff,0xef,0xfe,0xff,0xfd,0xff,0xff,0xff,0xff,
+ 0xbb,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xdb,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xe4,0x77,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xf7,0xbf,0xff,0xff,0xff,0xff,0xfe,
+ 0xec,0xaf,0xff,0xff,0xff,0xff,0xff,0xfb,0x3f,0xf3,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0x35,0xbf,0xff,0xff,0xff,0xff,0xff,0xf7,0x7f,0xf7,0xff,0xff,0xff,0xff,0xff,0xf5,
+ 0xa2,0x7f,0xff,0xff,0xf2,0xbf,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,
+ 0x12,0xdf,0xff,0xff,0xfd,0x7f,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+ 0x67,0xdf,0xaf,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
+ 0x43,0x7f,0x57,0xff,0xff,0x7f,0xff,0x77,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd8,
+ 0xb7,0xfe,0xbf,0xff,0xeb,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,
+ 0x3f,0xfd,0x7f,0xff,0xd7,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf2,
+ 0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdd,
+ 0x7f,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x81,
+ 0xfe,0xfb,0xfe,0xff,0xbf,0x6f,0xfb,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0x7e,0xd7,
+ 0xff,0xff,0xff,0xff,0xf6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xf6,0xeb,
+ 0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xdf,
+ 0xff,0xff,0xff,0xff,0xff,0x7f,0xdf,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0xbf,
+ 0xff,0xff,0xff,0xff,0xfb,0x7f,0x9f,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x3f,
+ 0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0xf7,
+ 0xff,0xe1,0xfe,0x7e,0x8f,0xa6,0xf1,0xee,0xdf,0xe7,0xf9,0xfe,0x7f,0x9f,0xcd,0xff,
+ 0xff,0xeb,0xff,0xfd,0xf7,0x6d,0xeb,0xdd,0xff,0xff,0xff,0xff,0xff,0xff,0x83,0xff,
+ 0xff,0xe7,0xff,0xfe,0xbf,0x9b,0xe7,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0x97,0xff,
+ 0xff,0x5f,0xff,0xfd,0xdf,0x77,0xdf,0x7d,0xff,0xff,0xff,0xff,0xff,0xfe,0xcd,0xff,
+ 0xfe,0xff,0xff,0xfe,0xf9,0xee,0x7e,0xef,0xff,0xff,0xff,0xff,0xff,0xfe,0x4f,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0x4f,0xff,0xff,0xef,0xff,0xff,0xff,0x7f,0xfe,0xbf,0xff,
+ 0xeb,0x7a,0xfe,0x3f,0xaf,0x6b,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,0xbf,0xf9,0x5f,0xff,
+ 0xfb,0xfb,0xff,0xdf,0xbf,0x3b,0xf3,0xdf,0xef,0xff,0xff,0xff,0xff,0xf6,0x7f,0xff,
+ 0xff,0xff,0xff,0xbf,0xea,0xed,0xbe,0xbf,0xff,0xff,0xfd,0xff,0xff,0x89,0xff,0xff,
+ 0xbf,0xff,0xff,0xff,0xff,0xf9,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xe1,0xfd,0xff,
+ 0xff,0xff,0xff,0xff,0xfd,0xfb,0xdf,0x7b,0xff,0xff,0xff,0xfd,0xfe,0x37,0xff,0xff,
+ 0xff,0xff,0xff,0xf7,0xff,0xf7,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xc7,0xff,0x7f,
+ 0xfb,0xfe,0xdf,0xf7,0xef,0xef,0xff,0xff,0xff,0x7f,0xff,0xff,0xf9,0xdf,0xff,0xef,
+ 0xc3,0xf3,0xdf,0xfd,0x3f,0xdf,0xbf,0xef,0xff,0xfb,0xff,0xff,0xdd,0x3f,0x7f,0xfd,
+ 0xff,0xfb,0xff,0xfe,0xfe,0xbf,0xff,0xff,0xff,0xfb,0xff,0xff,0xd3,0x7f,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0x1f,0xff,0xff,0xf8,0xfd,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xfd,0xff,0x9f,0x7f,
+ 0xff,0xff,0xff,0xfd,0xff,0xef,0xf7,0xff,0xff,0x7f,0xff,0xff,0xcb,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xfa,0xff,0xff,0xff,0xfb,0xfc,0xff,0xff,0xff,0x57,0xfa,0xff,0xff,
+ 0xff,0xff,0xff,0xd7,0xfb,0xff,0x7f,0xf7,0xfb,0xff,0xfe,0xff,0x6a,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xbe,0x7f,0x3f,0xff,0xbd,0xff,0xff,0xff,0xf6,0x5b,0xfa,0xff,0xff,
+ 0xff,0xff,0xff,0x3f,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0x5e,0x27,0xff,0xff,0xff,
+ 0xff,0xff,0xfe,0xb7,0xfe,0xce,0xd3,0xff,0xff,0xff,0xfe,0xf0,0x2d,0xff,0xff,0xff,
+ 0xff,0xff,0xfd,0x7f,0xff,0x9d,0xef,0xff,0xff,0xff,0xff,0x74,0x7f,0xff,0xfe,0xbf,
+ 0xaf,0xff,0xfa,0xed,0xff,0xff,0xeb,0xdf,0xf7,0xfd,0xff,0xac,0x3f,0xff,0xfd,0x5f,
+ 0x57,0xff,0xf7,0x6b,0xff,0xfd,0xf7,0xbf,0xff,0xff,0xfd,0xb3,0x7f,0xff,0xfa,0xfe,
+ 0xbf,0xff,0xeb,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xfe,0xb2,0xff,0xff,0xf5,0xfd,
+ 0x7f,0xff,0xdf,0xaf,0xff,0xdf,0xff,0xff,0x7f,0xdf,0xfe,0x2d,0x9f,0xff,0xff,0xff,
+ 0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xf9,0x97,0x7f,0xff,0xff,0xff,
+ 0xff,0xff,0xfe,0xbf,0xff,0xfb,0xff,0xf9,0xfe,0x7f,0xfd,0x9f,0xff,0xbf,0x6f,0xfb,
+ 0xfe,0xff,0xbe,0xfb,0xf6,0xf9,0xbf,0xe7,0xf9,0xd7,0xe2,0x7f,0xff,0xf6,0xff,0xff,
+ 0xff,0xfb,0xff,0xff,0x6f,0xf7,0xdf,0xff,0xff,0xef,0x68,0xbf,0xff,0xf7,0xff,0xff,
+ 0xff,0xbf,0xff,0xff,0x7f,0xff,0xff,0xef,0xfa,0xff,0xed,0xff,0xff,0xff,0x7f,0xff,
+ 0xff,0xfd,0xff,0xff,0xd7,0xfd,0xff,0x3f,0xef,0xff,0xd3,0xff,0x7f,0xfb,0x7f,0xff,
+ 0xff,0xe9,0xff,0xff,0x27,0xea,0xfe,0x3f,0xef,0xff,0xb3,0xff,0xff,0xfd,0xff,0xff,
+ 0xff,0xf7,0xff,0xfb,0x5f,0xf7,0xfd,0xff,0xff,0xff,0xef,0xff,0xff,0x8f,0x97,0xf1,
+ 0xfe,0x2f,0x9f,0xf8,0xb8,0x2e,0x9b,0xa7,0xf9,0xff,0x5f,0xff,0xff,0xf7,0x3f,0xef,
+ 0xff,0xc7,0xff,0xfd,0x3f,0xdf,0xf3,0x7e,0x7f,0xfc,0x3f,0xff,0xff,0xbf,0xdf,0xf7,
+ 0xfe,0xbf,0xff,0xf2,0xec,0xff,0xe7,0xff,0xff,0xf3,0x3f,0xff,0xff,0xdf,0x3f,0xef,
+ 0xff,0x7f,0xbf,0xe4,0xe7,0x75,0xdf,0x7f,0xff,0xee,0xef,0xff,0x7e,0xfb,0xff,0xff,
+ 0xfe,0x7f,0xff,0x6d,0x83,0xcb,0xb2,0xfd,0xff,0xdd,0xff,0xff,0xef,0xff,0xff,0xff,
+ 0xb6,0xff,0xff,0xfb,0xfe,0xff,0xff,0xff,0xff,0x83,0xff,0xfe,0xaf,0x8f,0xea,0xfa,
+ 0xf6,0xad,0xeb,0x7a,0xfe,0xbf,0xab,0xc3,0xff,0x35,0xff,0xfe,0xff,0xff,0xff,0xff,
+ 0xdd,0xff,0xff,0x4b,0x9e,0xff,0xff,0xff,0xfe,0x47,0xff,0xff,0xff,0xff,0xff,0xdf,
+ 0xfb,0xff,0xfe,0xef,0xff,0xff,0xbf,0xff,0xfa,0xdf,0xff,0xfb,0xff,0xff,0xef,0xff,
+ 0xff,0x9f,0xfb,0x7b,0xff,0xff,0xff,0xff,0xfd,0xbc,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xb7,0xff,0x78,0xff,0xb9,0xff,0xff,0xdf,0xe6,0x37,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xef,0x7d,0xfb,0xfd,0xff,0xff,0xff,0xdf,0xb2,0x7f,0xfc,0xef,0xff,0xff,0xdb,0x7b,
+ 0xfe,0xf7,0xff,0xbc,0xdf,0xff,0xef,0xff,0x84,0x7f,0xff,0xff,0xbd,0xf7,0x5f,0xf7,
+ 0xbd,0xff,0x7f,0x75,0xff,0xff,0xbf,0xff,0xc3,0xef,0xff,0xdf,0xff,0xfb,0xe7,0xfb,
+ 0xfb,0xfd,0x7b,0xfe,0xff,0xff,0xff,0xff,0x13,0xdf,0xff,0xff,0xf8,0x7e,0x3f,0xaf,
+ 0xe7,0xff,0xff,0xfb,0xff,0xff,0xff,0xfe,0x4f,0xb3,0xff,0xff,0xfd,0xff,0xdf,0xef,
+ 0xef,0xff,0xfd,0xff,0xff,0xff,0xff,0xfd,0xd5,0xff,0x5f,0xff,0xff,0xf6,0x7f,0xff,
+ 0xff,0xff,0xef,0xff,0xd7,0xfd,0xfe,0xff,0xaf,0xff,0xaf,0xff,0xff,0xfd,0xbf,0xf7,
+ 0xff,0xff,0xfa,0xbf,0xe7,0xf1,0xdb,0xf6,0x7f,0xfa,0xf7,0xff,0xff,0xff,0xdf,0xff,
+ 0xfe,0xff,0xff,0xdf,0xdf,0xef,0xfb,0xf6,0xbf,0xfb,0x75,0xc9,0xf3,0xec,0xff,0x5f,
+ 0xf3,0xed,0xcb,0xde,0xff,0xbf,0xff,0x55,0xaf,0xf5,0xff,0xf9,0xff,0xfb,0xff,0xff,
+ 0xf7,0xc7,0xf3,0xfd,0xff,0x7f,0xf5,0xd2,0x5f,0xeb,0xff,0xa6,0xaf,0xbf,0xff,0xfe,
+ 0xb7,0xaf,0xeb,0x7b,0xfe,0xff,0xef,0x36,0xfc,0xd7,0xff,0xe5,0x7f,0xff,0xff,0xbd,
+ 0x7f,0x5c,0xd7,0xf7,0xfd,0xf3,0xfe,0xa7,0xfd,0x2e,0xdf,0xff,0xff,0xff,0xaf,0xbf,
+ 0xfe,0xff,0xad,0xef,0xfa,0xff,0xfa,0xd3,0xff,0x57,0xbf,0xff,0x7f,0xda,0x57,0xff,
+ 0x7d,0xdf,0x56,0x9d,0xf5,0x7e,0xfd,0x36,0x7e,0xbc,0x7f,0xeb,0xff,0xfe,0xbd,0x6b,
+ 0xfa,0xfe,0xbf,0xbf,0xeb,0xff,0xf7,0x7e,0xfd,0x73,0xff,0xd7,0xff,0xfd,0x7f,0xd7,
+ 0xf5,0xe9,0x5f,0x7f,0xd7,0xff,0x20,0x7f,0xff,0xe7,0xff,0xff,0xff,0x9f,0xff,0xff,
+ 0xff,0xff,0x6d,0xff,0xff,0xff,0x85,0xff,0xff,0xe7,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xbe,0x6f,0xff,0xff,0xff,0xe9,0xff,0xfb,0xfe,0xff,0xbd,0x6f,0xfb,0xff,0xbf,
+ 0xec,0xd9,0xc6,0xff,0xb7,0x7e,0xa7,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xef,0xfe,
+ 0xff,0x3f,0xef,0xff,0xfc,0xf7,0xab,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xbf,0xfb,
+ 0xfb,0xfb,0xbf,0xff,0xef,0xff,0x1f,0xef,0x5f,0xff,0xff,0xef,0xff,0xff,0xfd,0xfd,
+ 0x7e,0x4f,0xf7,0xf5,0xff,0xff,0x3f,0xfe,0x9f,0xff,0xff,0xff,0x7f,0xff,0xed,0xf2,
+ 0x7e,0x8f,0x27,0xe9,0xff,0xf1,0x3f,0xfd,0x7f,0xfd,0xff,0x6f,0xff,0xff,0xf7,0xf5,
+ 0xfd,0x7f,0xdf,0xd7,0xff,0xfe,0xff,0xfa,0xe1,0xfa,0x7e,0x5f,0x97,0xe5,0xbe,0x4b,
+ 0x92,0xe8,0xba,0x2f,0x9f,0xf1,0xff,0xf5,0xff,0xfe,0xed,0xbb,0xfe,0xef,0xdd,0x93,
+ 0xf5,0xff,0x77,0x7f,0xff,0x8b,0xff,0xeb,0xf7,0xf9,0xdd,0x3f,0xdd,0xb6,0xff,0x2e,
+ 0xcb,0xea,0xfa,0xff,0xff,0x77,0xff,0xf7,0x1f,0xd7,0xfd,0xec,0x3f,0xcb,0x79,0x6e,
+ 0x17,0x5d,0xf5,0xff,0xfe,0x8f,0xff,0xaf,0x1f,0x9f,0x77,0xdb,0xf6,0xfb,0xef,0x99,
+ 0xec,0xeb,0xfb,0xff,0xfe,0xcb,0xf5,0xcf,0xff,0xff,0x7d,0x3f,0xff,0xff,0xfd,0xff,
+ 0xef,0xc9,0xf7,0xff,0xf6,0xbf,0xff,0xea,0xfa,0xfe,0xbd,0xaf,0xeb,0xde,0xad,0xab,
+ 0xea,0xfa,0xee,0xbf,0xf8,0x5f,0xff,0xf7,0xff,0xff,0xfc,0xff,0xff,0xf3,0xfc,0xfd,
+ 0x1b,0xbf,0xbf,0xff,0x26,0x7f,0xff,0x3f,0xff,0xff,0xf6,0xf7,0xff,0xbd,0xfa,0xfb,
+ 0xff,0xff,0xff,0x7d,0xa9,0xff,0xff,0xfb,0xfe,0xff,0xaf,0xff,0xbd,0xdf,0xdb,0xfb,
+ 0xff,0xff,0xff,0xff,0xe3,0xdf,0xeb,0xff,0xff,0xff,0xbb,0xff,0xbd,0xf7,0xff,0xfb,
+ 0xff,0xfc,0xbe,0xfe,0x13,0xff,0xdb,0xff,0xff,0xff,0xef,0x7f,0xb7,0xde,0xff,0xff,
+ 0xff,0xff,0x7f,0xfe,0xa6,0xf7,0xfb,0xff,0xff,0xeb,0xfb,0x7e,0xef,0xe5,0xff,0xbf,
+ 0xbf,0xf8,0xff,0xf8,0xcb,0xff,0x7f,0xff,0xff,0xf7,0xbf,0xec,0xde,0xff,0xbf,0xff,
+ 0xff,0xb7,0x7f,0xfb,0x3f,0xfe,0xff,0xff,0xff,0xff,0xff,0xfe,0xbf,0xd7,0xf7,0xff,
+ 0xff,0xef,0xfd,0xf8,0x3f,0xff,0xfb,0xff,0xff,0xef,0xfb,0xfa,0x3e,0xff,0xdc,0xff,
+ 0xff,0xb9,0x7b,0xea,0xff,0xff,0xff,0xff,0xff,0x7e,0x7f,0xfe,0xff,0xff,0xfa,0xfb,
+ 0xef,0xff,0x77,0xc1,0xff,0xfd,0xff,0xff,0xdf,0xd7,0xdf,0xff,0x5f,0xd3,0x7f,0xcf,
+ 0xf7,0xfd,0xff,0xf3,0xff,0x77,0xbf,0xff,0x3f,0xef,0xfe,0xff,0xef,0xeb,0xff,0xdf,
+ 0xff,0xff,0xef,0xe7,0xfb,0xff,0xff,0xfe,0xff,0xbf,0xfe,0xff,0xef,0xbd,0xff,0xff,
+ 0xff,0xff,0x76,0x4c,0x5f,0xdd,0xf5,0xff,0xff,0x7f,0xb7,0xff,0x5f,0xd7,0xf9,0xff,
+ 0xff,0xff,0xfc,0x1f,0x5f,0xbf,0xdf,0xf6,0xff,0xff,0xef,0xfe,0xff,0xff,0xef,0xed,
+ 0xf7,0xfd,0xff,0x8f,0xfe,0xff,0xff,0xff,0xff,0xfe,0xff,0xec,0xff,0x3e,0xfd,0x73,
+ 0xff,0xff,0xf6,0x6b,0xfc,0x6f,0xff,0xff,0xad,0xbc,0xff,0xd7,0x9f,0xfd,0xf3,0xff,
+ 0xff,0xfd,0xe4,0xf7,0xfa,0xfe,0xbf,0xfe,0x7f,0xca,0xff,0xbb,0x4a,0xfb,0xff,0xef,
+ 0xff,0x5b,0xc1,0xbf,0x97,0xed,0x7f,0xff,0xff,0x95,0xff,0x5c,0xd7,0xf7,0xff,0xff,
+ 0xfe,0xff,0x9b,0xff,0xeb,0xa7,0xff,0xff,0xff,0xeb,0xfe,0xff,0x7f,0xef,0x7f,0xfe,
+ 0xbe,0xfe,0x84,0xff,0xd5,0xef,0x7f,0xff,0xd7,0xdd,0x6d,0x5c,0xf7,0xdd,0xff,0xfd,
+ 0x5f,0xf6,0x0d,0xff,0xaf,0xab,0xff,0xdf,0xff,0xaf,0xfb,0xfa,0xbf,0xbb,0xff,0xfa,
+ 0xfe,0x6d,0x5f,0xff,0x5f,0xd7,0xff,0xff,0xff,0x5f,0xf5,0xfd,0x7f,0x7e,0xbf,0xf5,
+ 0xfd,0xfd,0xbe,0xef,0xf9,0xff,0xff,0xff,0xed,0xff,0xff,0xb7,0xff,0xdf,0xff,0xff,
+ 0xff,0xe9,0x7f,0xeb,0xf9,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xef,0x9f,0xff,0xff,
+ 0xff,0x7e,0x7f,0xb6,0xfd,0xbf,0xef,0xdb,0x6e,0xdf,0xed,0xfb,0xee,0x3f,0xbf,0xef,
+ 0xff,0xb9,0xbf,0x6f,0xdb,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0x83,0xfe,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xfd,0xd5,0xff,0xd7,0xfd,0xff,0x7f,0xff,0xff,0xff,0x7b,0x5e,0xf9,0xff,0xff,0xff,
+ 0xfe,0x2f,0xff,0xa7,0xed,0xfe,0xbf,0xdf,0xf7,0xfe,0x7c,0x9f,0xfb,0xff,0xff,0xff,
+ 0xef,0x1f,0xff,0x5f,0xf7,0xfd,0xff,0xff,0xff,0xff,0xfd,0x7f,0xf5,0xff,0xff,0xff,
+ 0xf5,0x3f,0xfe,0xbe,0x3e,0x1b,0xe6,0xf1,0xfe,0x7b,0xa2,0xed,0xfc,0x7e,0xdf,0xa7,
+ 0xfc,0x7f,0xfd,0x7f,0xdc,0xff,0xff,0xfd,0xff,0xf7,0xfe,0xff,0xbb,0xff,0xff,0x7f,
+ 0xf8,0xff,0xfa,0xfe,0xff,0x7f,0xff,0xd6,0xfb,0xef,0xff,0xff,0x7d,0xff,0xff,0xfb,
+ 0xc9,0xff,0xf5,0xff,0x7d,0xff,0xff,0xf7,0xfe,0xfd,0x73,0x5f,0xfb,0xf5,0xff,0x7f,
+ 0x2b,0xff,0xfb,0xfb,0xf1,0xf7,0xf7,0x5b,0xbf,0xbe,0xe6,0xff,0x7f,0xef,0xfe,0xfb,
+ 0x93,0xff,0x53,0xff,0xff,0xfd,0x7f,0x52,0xdf,0xbf,0xff,0xeb,0xff,0xff,0xff,0xff,
+ 0x8f,0xff,0xfa,0xfe,0xbf,0xae,0xeb,0xda,0x37,0xaf,0xeb,0xfa,0xfe,0xbf,0xaf,0xfe,
+ 0x57,0xff,0xbf,0x7f,0xff,0x7b,0xff,0xff,0xf7,0xef,0x7f,0xff,0xff,0xff,0xff,0xaf,
+ 0x1e,0xff,0xef,0xff,0xff,0xbf,0xeb,0xff,0x7e,0xff,0xbf,0xff,0xff,0xff,0xff,0xed,
+ 0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xd6,0x7f,0xfb,0xdf,0xff,0xff,0xff,0xfb,0x6a,
+ 0x7f,0xfa,0xff,0xdf,0xef,0xf9,0xfb,0xff,0x7e,0xa3,0xff,0xf7,0xff,0xff,0xfb,0xd9,
+ 0xff,0xfa,0xff,0xff,0xbf,0xdf,0xde,0xf5,0xff,0xed,0xff,0xff,0xff,0xff,0xff,0x51,
+ 0xff,0xff,0xff,0xef,0xbb,0xef,0xff,0xfb,0xff,0xfa,0xfd,0xff,0xfb,0xff,0xf6,0x57,
+ 0xff,0xff,0xff,0xfc,0xf7,0x37,0xfe,0xf5,0xff,0xff,0xbf,0xef,0xf7,0xbf,0xfc,0x0f,
+ 0xff,0xff,0xff,0xfb,0xfe,0xff,0xff,0x6e,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x9f,
+ 0xff,0xff,0xff,0xff,0xf7,0xdf,0xff,0xcf,0x6f,0xfe,0xfe,0xbf,0xbf,0xdf,0xe7,0xbb,
+ 0xff,0xff,0xff,0xff,0xbf,0xf9,0xef,0xbf,0xe7,0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,
+ 0xdf,0xff,0xff,0xff,0xfd,0x7f,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xbe,0xf4,0xff,
+ 0xdf,0xef,0xff,0xff,0xf3,0xff,0xdd,0xef,0xff,0xff,0xff,0xff,0xff,0xfd,0xe5,0xf7,
+ 0xff,0xff,0xff,0xfe,0xf7,0xff,0xfe,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0x9a,0xff,
+ 0xff,0xff,0xff,0xff,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe6,0xbf,
+ 0xff,0xff,0xff,0xef,0xde,0x97,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x5e,0x49,0x7f,
+ 0xff,0xff,0xff,0xfe,0xfd,0x2f,0x5f,0xff,0xff,0xff,0xff,0xff,0xe6,0xbc,0x1b,0xff,
+ 0xff,0xff,0xff,0xff,0x7f,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfa,0x9f,0xf5,
+ 0xff,0xff,0xeb,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xe8,0x6f,0xff,
+ 0xff,0xff,0xd5,0xff,0x7d,0x5e,0xfd,0xff,0xff,0xff,0xff,0xff,0xfb,0x72,0x7f,0xff,
+ 0xff,0xff,0xaf,0xff,0xfa,0xdb,0xef,0xff,0xff,0xff,0xff,0xff,0xf6,0xc5,0xff,0xff,
+ 0xff,0xff,0x5f,0xff,0xf5,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xa1,0xfe,0xff,
+ 0xff,0xff,0xff,0xfe,0xdf,0xb7,0xfb,0xff,0xff,0xff,0xff,0xff,0xfe,0x57,0xfe,0xbf,
+ 0xff,0xff,0xff,0xfe,0xfd,0x9f,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xe7,0xfb,0xef,
+ 0xfb,0xfe,0xfd,0xb6,0xed,0xde,0xdb,0xbf,0xef,0xfb,0xf6,0xff,0xf8,0xdf,0xff,0xff,
+ 0xff,0xff,0xf3,0xff,0xff,0x3f,0xff,0xff,0xff,0xff,0x6f,0xff,0xf8,0xaf,0xff,0xff,
+ 0xff,0xff,0xbf,0xff,0xee,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xd2,0x7f,0xff,0xff,
+ 0xff,0xff,0xe5,0xff,0xff,0xd7,0xff,0xff,0xff,0xff,0xf7,0xbf,0xf4,0xff,0xff,0xff,
+ 0xff,0xff,0xe9,0xdf,0xb5,0xa7,0xff,0xff,0xff,0xff,0xb7,0xff,0xd4,0xff,0xff,0xff,
+ 0xff,0xff,0xd7,0xfd,0xff,0x5f,0xff,0xff,0xff,0xff,0xdf,0xff,0x0b,0xff,0xff,0xe7,
+ 0xe1,0xfe,0x3f,0x0f,0xe6,0xbe,0x7f,0xdf,0xe7,0xf8,0xfa,0x7f,0x47,0xff,0xff,0xff,
+ 0xff,0xff,0x5f,0xff,0xfd,0x3f,0xff,0xff,0xff,0xff,0x77,0xff,0x0f,0xff,0xff,0xff,
+ 0xf7,0xfe,0xbf,0x7f,0xfa,0xff,0xff,0xff,0xdf,0xfb,0xff,0xfe,0xdf,0xff,0xff,0xff,
+ 0x1f,0xff,0x7b,0xdf,0xe4,0xf7,0xfd,0xff,0xff,0xdd,0xf7,0xfe,0x3f,0xfd,0xff,0xfe,
+ 0x1f,0xfb,0xf4,0xf7,0xed,0xef,0xff,0xfd,0x7e,0xaf,0xaf,0xf5,0x7f,0xff,0xff,0xff,
+ 0xff,0xff,0xfd,0xbb,0xfa,0xff,0xff,0xef,0xff,0xff,0xfe,0xd8,0xff,0xff,0xaf,0xeb,
+ 0xfa,0xfe,0xbf,0xaf,0x7a,0xfe,0xbf,0xaf,0xeb,0xfa,0xff,0xcd,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xf3,0x5f,0x4f,0xff,0xff,0xf7,0xff,0xff,0xfe,0x91,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xdf,0xfe,0xe9,0xfe,0x7f,0xef,0xfb,0xfd,0xfe,0xb7,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0x7d,0xc7,0x77,0xf7,0xff,0xbf,0xff,0xff,0xee,0x07,0xff,0xff,0xff,0xff,
+ 0xfe,0x3f,0xff,0xf3,0xff,0xff,0xf7,0xff,0xff,0xff,0xbc,0x9f,0xff,0xff,0xff,0xff,
+ 0xfd,0xfd,0xff,0xdd,0x7b,0xff,0xff,0xff,0xff,0xff,0xf0,0x1f,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xbf,0xb3,0xff,0xff,0xff,0xfd,0xfe,0xff,0x68,0x7f,0xff,0xff,0xff,0xff,
+ 0xff,0x7c,0xbf,0x57,0xfe,0xff,0xff,0xff,0xff,0xfd,0xca,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xbe,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xf5,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x43,0xff,0xff,0xbf,0xff,0xff,
+ 0xff,0xbf,0xfb,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0x97,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xbd,0xdf,0xff,0xff,0xff,0xff,0xfe,0x2f,0xff,0xff,0xff,0xff,0xff,
+ 0xfe,0xeb,0xf7,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,0xff,0xff,0xbf,0xff,
+ 0xff,0xdd,0xff,0xfd,0x7f,0xff,0xff,0xff,0xff,0xfa,0x2f,0xff,0xff,0xff,0xff,0xff,
+ 0xfe,0xff,0xef,0x7b,0x3f,0xff,0xff,0xff,0xff,0xcb,0x6b,0xff,0xff,0xff,0xff,0xff,
+ 0xfc,0xff,0xdf,0xf1,0x7c,0xff,0xff,0xff,0xfd,0x74,0xf7,0xff,0xff,0xff,0xff,0xff,
+ 0xca,0xff,0xaf,0x4f,0xfe,0xdf,0xff,0xff,0xfb,0xdd,0xbf,0xff,0xff,0xff,0xff,0xff,
+ 0x95,0xff,0x5e,0xf7,0xf7,0xff,0xff,0xff,0xfd,0xc1,0xef,0xdf,0xff,0xff,0xff,0xff,
+ 0xeb,0xff,0xfe,0xaf,0x5b,0xff,0xff,0xff,0xff,0x46,0xff,0x3f,0xff,0xff,0xff,0xff,
+ 0xd5,0x6f,0xff,0x57,0x9d,0xef,0xff,0xff,0xf6,0xa7,0xfe,0xff,0xff,0xff,0xff,0xff,
+ 0xaf,0xfa,0xfe,0xf4,0x6f,0xbf,0xff,0xff,0xf9,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0x5f,0xf5,0xff,0x7b,0x7f,0xff,0xff,0xff,0xf9,0x9f,0xef,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0x9f,0xeb,0xff,0xff,0xff,0xff,0xf5,0x7f,0xfb,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xfd,0x9f,0xfb,0xff,0xff,0xff,0xff,0xee,0x7f,0xfe,0xff,0xbf,0xef,0xfb,0xfe,
+ 0xdf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xad,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xfb,0xff,0xbf,0xff,0xff,0xff,0xff,0xfd,0xab,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xef,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0x87,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+ 0xfd,0x7f,0x5f,0xff,0xff,0xff,0xff,0xfe,0x0f,0xff,0xff,0xff,0xff,0xff,0xff,0xe7,
+ 0xfa,0xaf,0xdf,0xff,0xff,0xff,0xff,0xfd,0x1f,0xff,0xff,0xff,0xff,0xff,0xfe,0xde,
+ 0xf5,0xcb,0xff,0xff,0xff,0xff,0xfb,0xf2,0xbf,0xff,0xfe,0x7f,0x9f,0xe7,0xf9,0xbe,
+ 0x6b,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xef,0x7f,0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,
+ 0xff,0xfe,0x7f,0xff,0xff,0xff,0xff,0xe2,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0xff,0xef,0xff,0xff,0xff,0xff,0xf5,0xfe,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,
+ 0xb7,0xf7,0xff,0xff,0xff,0xff,0xff,0x87,0xff,0xff,0xff,0xff,0xff,0xff,0xd3,0xfd,
+ 0x9d,0xff,0xff,0xff,0xff,0xff,0xfd,0xcf,0xff,0xfa,0xfe,0xbf,0xaf,0xeb,0xda,0xf7,
+ 0xaf,0xeb,0xfa,0xbe,0xbf,0xaf,0xfd,0x5e,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0xf3,
+ 0x7f,0x3f,0xff,0xff,0xdf,0xff,0xfe,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,
+ 0xf2,0xbf,0xff,0xff,0xff,0xdf,0xe2,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,
+ 0xdf,0xfb,0xbc,0xf7,0xff,0xff,0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xfb,0x7f,0xef,
+ 0xef,0xff,0xff,0xdf,0xff,0xff,0xd1,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xfd,0xbf,
+ 0xfb,0x7f,0xff,0xff,0xff,0xff,0xe9,0xff,0xff,0xff,0xef,0xfb,0xf3,0xff,0xfb,0xf7,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x27,0xff,0xfb,0xff,0xff,0xbf,0xff,0xff,0xf7,0xff,
+ 0xff,0xff,0xf7,0xff,0xff,0xfe,0x0f,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,0xdf,
+ 0xfd,0xff,0xfb,0xff,0xff,0xfe,0x5b,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,
+ 0xff,0xff,0xd7,0xff,0xff,0xfb,0xbf,0xff,0xff,0xff,0xff,0xdf,0xff,0xeb,0xbf,0xff,
+ 0xbf,0xff,0xff,0xff,0xff,0xf4,0x7f,0xdf,0xff,0xff,0xff,0xff,0xef,0xf9,0xff,0xff,
+ 0xff,0xff,0xdf,0xff,0xff,0xf2,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xe7,0xfb,
+ 0xff,0xff,0xbf,0xff,0xff,0x9d,0xfb,0xff,0xff,0xff,0xff,0xff,0xbf,0xfe,0xbf,0xf7,
+ 0xff,0xf8,0xff,0xff,0xff,0xb0,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xfc,0xa6,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0x9f,0xff,0xff,0xd6,0x0f,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,
+ 0xff,0x3f,0xff,0xff,0xbc,0x5b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xfe,0xef,0xff,0xff,0xdf,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0x7f,0xff,
+ 0xfe,0xf7,0xff,0xff,0xfd,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,
+ 0xff,0xf5,0xbf,0xff,0x6e,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xa5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xfd,0xbf,0xff,0xff,0x93,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xb7,0x67,0xff,0xdf,0x67,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,
+ 0xff,0xff,0xff,0xfe,0x67,0xff,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xde,0xef,0xbf,0xef,
+ 0xf9,0x7e,0xff,0xf9,0x1b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x3f,0x7f,0xff,0xff,
+ 0xff,0xff,0xff,0xdb,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd7,0xfd,0xfd,0x7f,
+ 0xc7,0xff,0xff,0xba,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xab,0xf9,0xf2,0x7f,
+ 0xbf,0xff,0xff,0xc8,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0x5d,0xf7,0xff,0xff,
+ 0x7f,0xff,0xff,0xeb,0xff,0xff,0xe7,0xf9,0xfe,0x7f,0x9f,0xe6,0xbe,0x6f,0x9f,0xe6,
+ 0x79,0xfe,0x7f,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xd7,0xfd,
+ 0xff,0xff,0xfe,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xaf,0xfb,
+ 0xff,0xff,0xfe,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0x7f,0xff,0xf7,
+ 0xff,0xff,0xf1,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x7e,0xff,0xff,0xff,
+ 0xff,0xff,0x7d,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdb,0xff,0xff,0xff,0x4f,
+ 0xff,0xff,0xd0,0xff,0xff,0xaf,0xeb,0xfa,0xfe,0xbf,0xaf,0x7a,0xfe,0xbf,0xaf,0x4b,
+ 0xfa,0xbf,0xd1,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x37,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0x81,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xbf,
+ 0xff,0xfe,0x97,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xfe,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfa,0xef,0xff,0xfd,0xeb,0xff,
+ 0xff,0xfd,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd9,0xff,0xff,0xf5,0xeb,0xff,
+ 0xff,0xff,0x1d,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbd,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xf8,0x37,0xfb,0xbf,0xff,0xfb,0xff,0xff,0x9f,0x3f,0xff,0xfb,0xff,0xff,0xff,
+ 0xff,0xe2,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xfe,0xff,0xff,0xf7,0xff,0xff,0xff,
+ 0xff,0xd0,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xbb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xfe,0xfb,0xff,0xff,0xff,0xff,
+ 0xff,0xc7,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xcf,0xfb,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xfb,0x5f,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0x8f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xc6,0x6b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
+ 0x6c,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
+ 0xf9,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
+ 0xa3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0x26,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+ 0x07,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
+ 0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0x3f,0xe7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+ 0x7f,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,
+ 0x7f,0xee,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xb9,
+ 0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xbb,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x47,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xfe,0x8d,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x8f,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0x3f,
+ 0xff,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf2,0x7f,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe4,0xf7,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc9,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xa3,0xdf,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0x57,0xbf,
+ 0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xdf,0xce,0xff,
+ 0xfa,0x7e,0xbf,0xaf,0xeb,0xfa,0xff,0xaf,0xea,0xfa,0xfc,0xaf,0xaf,0xd5,0x5d,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xfb,0xff,0xff,0xff,0xff,0xff,0xfd,0x1f,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe9,0x7f,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x3d,0xef,0xf3,0xff,0xff,0xff,0xff,0xec,0x7f,0xff,
+ 0xff,0xff,0xfe,0xff,0xff,0xfe,0xff,0xfe,0xff,0xff,0xff,0xfb,0xff,0xcd,0xff,0xff,
+ 0xff,0xf7,0xfd,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe1,0xff,0xff,
+ 0xf4,0xff,0xff,0xff,0xf3,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,
+ 0xff,0xff,0xff,0xfd,0xdf,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x2f,0xff,0xff,
+ 0xff,0xff,0xdf,0xf7,0xef,0xeb,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x1f,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xbf,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xfd,0xbf,0xff,0xff,0xff,0xfd,0xff,0xff,0xf0,0x7f,0xff,0xff,
+ 0x5d,0xf7,0xff,0xff,0xf5,0xbf,0xff,0xff,0xff,0xff,0xfd,0xff,0xf4,0xff,0xfe,0xff,
+ 0xbf,0xcf,0xff,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x99,0xff,0xfb,0xef,
+ 0x7f,0xdf,0xfe,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xbf,0xf9,0xf8,
+ 0x7f,0x9f,0xe7,0xf9,0xff,0x9f,0xe7,0xe1,0xfe,0x7f,0x9f,0xee,0xa7,0xff,0xfb,0xfa,
+ 0xde,0xbf,0xef,0xfb,0xdf,0xbf,0xef,0xeb,0xfe,0xfe,0xaf,0xfe,0x4f,0xff,0x6e,0xfb,
+ 0xff,0xff,0xbf,0xef,0xb7,0xff,0xbd,0xef,0xfb,0xee,0xff,0xff,0x1f,0xff,0xff,0xbf,
+ 0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xbf,0xff,0xbf,0xff,
+ 0xff,0xfe,0xff,0xfd,0xfb,0xfe,0xff,0xbf,0xef,0xbb,0x3f,0xff,0x7f,0xfc,0x7f,0x1f,
+ 0xc5,0xf1,0x7c,0x7d,0xcf,0xf3,0xfc,0xff,0x3f,0x4f,0xff,0xec,0xef,0xfa,0xfe,0xff,
+ 0xbf,0xeb,0xfb,0xfb,0xbf,0xaf,0xfb,0xfe,0xff,0xbf,0x7f,0xc9,0xff,0xf9,0xfe,0xff,
+ 0xbf,0xe7,0xfb,0xff,0xb7,0xe5,0xf9,0x7e,0x5f,0x97,0xff,0xc3,0xff,0xf7,0xfd,0xff,
+ 0x7f,0xdf,0xf7,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xff,0x07,0xff,0xff,0xfc,0xff,
+ 0x7f,0xff,0xf3,0xdf,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,0xff,0xdf,0xf7,0xfd,
+ 0xf7,0x7e,0xdf,0xed,0xff,0x7f,0xdf,0xf7,0xfd,0xf7,0xfd,0x1f,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0x5e,0xf7,0xff,0xff,0xff,0xff,0xff,0xfa,0x3f,0xff,0xdf,0xf7,0xfd,
+ 0xff,0x7f,0xde,0xfd,0xef,0x7f,0xdf,0xf7,0xfd,0xff,0xf0,0x7b,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xfd,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xfa,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xfe,0xff,0xff,
+ 0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xbf,0xfb,0xa3,0xff,0xff,0xff,0xff,0xfe,
+ 0xff,0xb7,0xff,0x7f,0xff,0xff,0xfd,0xfb,0xff,0xff,0x67,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xff,0xff,0xff,0x6f,0xff,0xff,0xff,0xff,0xfd,
+ 0xff,0x3f,0xeb,0xff,0xff,0xff,0xff,0xff,0xfe,0xfc,0x9f,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xdf,0xff,0xff,0xff,0xdf,0xef,0xfe,0xfe,0xbf,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xf5,0x7f,0xff,0xfb,0xfe,0xff,0x8f,
+ 0xe0,0xfb,0xcf,0xbf,0xef,0xfb,0x3e,0x3f,0xbf,0xf8,0xff,0xfc,0xff,0x3f,0xcf,0xdb,
+ 0xf0,0xfe,0x8f,0xfb,0xfe,0xfe,0x3f,0x6f,0xff,0xd9,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xbd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x93,0xff,0xff,0xef,0xbb,0xee,0xbf,
+ 0xbf,0xef,0xee,0xbb,0xef,0xff,0xfa,0xef,0xff,0x87,0xff,0x76,0xbd,0xaf,0x6f,0xbb,
+ 0xfd,0xbf,0xfb,0xff,0xbd,0xef,0xff,0xfe,0xa5,0x4f,0xff,0xff,
--- /dev/null
+//------------------------------------------------------------------------------+
+//
+// This source code has been made available to you by IBM on an AS-IS
+// basis. Anyone receiving this source is licensed under IBM
+// copyrights to use it in any way he or she deems fit, including
+// copying it, modifying it, compiling it, and redistributing it either
+// with or without modifications. No license under IBM patents or
+// patent applications is to be implied by the copyright license.
+//
+// Any user of this software should understand that IBM cannot provide
+// technical support for this software and will not be responsible for
+// any consequences resulting from the use of this software.
+//
+// Any person who transfers this source code or any derivative work
+// must include the IBM copyright notice, this paragraph, and the
+// preceding two paragraphs in the transferred software.
+//
+// COPYRIGHT I B M CORPORATION 1995
+// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+//-------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Function: ext_bus_cntlr_init
+// Description: Initializes the External Bus Controller for the external
+// peripherals. IMPORTANT: For pass1 this code must run from
+// cache since you can not reliably change a peripheral banks
+// timing register (pbxap) while running code from that bank.
+// For ex., since we are running from ROM on bank 0, we can NOT
+// execute the code that modifies bank 0 timings from ROM, so
+// we run it from cache.
+// Bank 0 - Flash bank 0
+// Bank 1 - Flash bank 1
+// Bank 2 - CAN0, CAN1, CAN2, Codeswitch (0x000,0x100,0x200,0x400)
+// Bank 3 - IDE (CompactFlash)
+// Bank 4 - Quart
+// Bank 5 - not used
+// Bank 6 - not used
+// Bank 7 - not used
+//-----------------------------------------------------------------------------
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+ .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+ mflr r4 // save link register
+ bl ..getAddr
+..getAddr:
+ mflr r3 // get address of ..getAddr
+ mtlr r4 // restore link register
+ addi r4,0,14 // set ctr to 10; used to prefetch
+ mtctr r4 // 10 cache lines to fit this function
+ // in cache (gives us 8x10=80 instrctns)
+..ebcloop:
+ icbt r0,r3 // prefetch cache line for addr in r3
+ addi r3,r3,32 // move to next cache line
+ bdnz ..ebcloop // continue for 10 cache lines
+
+ //-------------------------------------------------------------------
+ // Delay to ensure all accesses to ROM are complete before changing
+ // bank 0 timings. 200usec should be enough.
+ // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ //-------------------------------------------------------------------
+ addis r3,0,0x0
+ ori r3,r3,0xA000 // ensure 200usec have passed since reset
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp // spin loop
+
+ //-----------------------------------------------------------------------
+ // Memory Bank 0 (Flash Bank 0) initialization
+ //-----------------------------------------------------------------------
+ addi r4,0,pb0ap
+ mtdcr ebccfga,r4
+ addis r4,0,0x9201
+ ori r4,r4,0x5480
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb0cr
+ mtdcr ebccfga,r4
+ addis r4,0,0xFFC5 // BAS=0xFFC,BS=0x2(4MB),BU=0x3(R/W),
+ ori r4,r4,0xA000 // BW=0x1(16 bits)
+ mtdcr ebccfgd,r4
+
+ //-----------------------------------------------------------------------
+ // Memory Bank 1 (Flash Bank 1) initialization
+ //-----------------------------------------------------------------------
+ addi r4,0,pb1ap
+ mtdcr ebccfga,r4
+ addis r4,0,0x9201
+ ori r4,r4,0x5480
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb1cr
+ mtdcr ebccfga,r4
+ addis r4,0,0xFF85 // BAS=0xFF8,BS=0x2(4MB),BU=0x3(R/W),
+ ori r4,r4,0xA000 // BW=0x1(16 bits)
+ mtdcr ebccfgd,r4
+
+ //-----------------------------------------------------------------------
+ // Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization
+ //-----------------------------------------------------------------------
+ addi r4,0,pb2ap
+ mtdcr ebccfga,r4
+ addis r4,0,0x0100
+ ori r4,r4,0x53c0 // enable Ready, BEM=1
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb2cr
+ mtdcr ebccfga,r4
+ addis r4,0,0xF001 // BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),
+ ori r4,r4,0x8000 // BW=0x0(8 bits)
+ mtdcr ebccfgd,r4
+
+ //-----------------------------------------------------------------------
+ // Memory Bank 3 (CompactFlash IDE) initialization
+ //-----------------------------------------------------------------------
+ addi r4,0,pb3ap
+ mtdcr ebccfga,r4
+ addis r4,0,0x0100
+ ori r4,r4,0x53c0 // enable Ready, BEM=1
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb3cr
+ mtdcr ebccfga,r4
+ addis r4,0,0xF011 // BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),
+ ori r4,r4,0xA000 // BW=0x1(16 bits)
+ mtdcr ebccfgd,r4
+
+ //-----------------------------------------------------------------------
+ // Memory Bank 4 (NVRAM) initialization
+ //-----------------------------------------------------------------------
+ addi r4,0,pb4ap
+ mtdcr ebccfga,r4
+ addis r4,0,0x0100
+ ori r4,r4,0x5280 // disable Ready, BEM=0
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb4cr
+ mtdcr ebccfga,r4
+ addis r4,0,0xF021 // BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),
+ ori r4,r4,0x8000 // BW=0x0(8 bits)
+ mtdcr ebccfgd,r4
+
+ //-----------------------------------------------------------------------
+ // Memory Bank 5 (Quart) initialization
+ //-----------------------------------------------------------------------
+ addi r4,0,pb5ap
+ mtdcr ebccfga,r4
+ addis r4,0,0x0100
+ ori r4,r4,0x5280 // disable Ready, BEM=0
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb5cr
+ mtdcr ebccfga,r4
+ addis r4,0,0xF031 // BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),
+ ori r4,r4,0x8000 // BW=0x0(8 bits)
+ mtdcr ebccfgd,r4
+
+ cmpi cr0,0,r9,0x0 // check if I cache was off when we
+ // started
+ bne ..ebc_done // if it was on, leave on
+ addis r4,r0,0x0000 // if it was off, disable
+ mticcr r4 // restore iccr
+ isync
+..ebc_done:
+ nop // pass2 DCR errata #8
+ blr
+
+//-----------------------------------------------------------------------------
+// Function: sdram_init
+// Description: Configures SDRAM memory banks.
+// Auto Memory Configuration option reads the SDRAM EEPROM
+// via the IIC bus and then configures the SDRAM memory
+// banks appropriately. If Auto Memory Configuration is
+// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
+// plugged, ie. the DIMM that shipped wih the Eval board.
+//-----------------------------------------------------------------------------
+ .globl sdram_init
+
+sdram_init:
+
+ mflr r31
+
+ //-------------------------------------------------------------------
+ // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
+ //-------------------------------------------------------------------
+ addi r4,0,mem_mb0cf
+ mtdcr memcfga,r4
+ addis r4,0,0x0004
+ ori r4,r4,0x6001
+ mtdcr memcfgd,r4
+
+ //-------------------------------------------------------------------
+ // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
+ // To set the appropriate timings, we need to know the SDRAM speed.
+ // We can use the PLB speed since the SDRAM speed is the same as
+ // the PLB speed. The PLB speed is the FBK divider times the
+ // 405GP reference clock, which on the Walnut board is 33Mhz.
+ // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is
+ // 100Mhz; if FBK is 3, SDRAM is 133Mhz.
+ // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and
+ // maybe 133Mhz.
+ //-------------------------------------------------------------------
+ mfdcr r5,strap // determine FBK divider
+ // via STRAP reg to calc PLB speed.
+ // SDRAM speed is the same as the PLB
+ // speed.
+ rlwinm r4,r5,4,0x3 // get FBK divide bits
+
+..chk_66:
+ cmpi %cr0,0,r4,0x1
+ bne ..chk_100
+ addis r6,0,0x0085 // SDTR1 value for 66Mhz
+ ori r6,r6,0x4005
+ addis r7,0,0x03F8 // RTR value for 66Mhz
+ b ..sdram_ok
+..chk_100:
+ cmpi %cr0,0,r4,0x2
+ bne ..chk_133
+ addis r6,0,0x0086 // SDTR1 value for 100Mhz
+ ori r6,r6,0x400D
+ addis r7,0,0x05F0 // RTR value for 100Mhz
+ b ..sdram_ok
+..chk_133:
+ addis r6,0,0x0107 // SDTR1 value for 133Mhz
+ ori r6,r6,0x4015
+ addis r7,0,0x07F0 // RTR value for 133Mhz
+
+..sdram_ok:
+ //-------------------------------------------------------------------
+ // Set SDTR1
+ //-------------------------------------------------------------------
+ addi r4,0,mem_sdtr1
+ mtdcr memcfga,r4
+ mtdcr memcfgd,r6
+
+ //-------------------------------------------------------------------
+ // Set RTR
+ //-------------------------------------------------------------------
+ addi r4,0,mem_rtr
+ mtdcr memcfga,r4
+ mtdcr memcfgd,r7
+
+ //-------------------------------------------------------------------
+ // Delay to ensure 200usec have elapsed since reset. Assume worst
+ // case that the core is running 200Mhz:
+ // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ //-------------------------------------------------------------------
+ addis r3,0,0x0000
+ ori r3,r3,0xA000 // ensure 200usec have passed since reset
+ mtctr r3
+..spinlp2:
+ bdnz ..spinlp2 // spin loop
+
+ //-------------------------------------------------------------------
+ // Set memory controller options reg, MCOPT1.
+ // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
+ // read/prefetch.
+ //-------------------------------------------------------------------
+ addi r4,0,mem_mcopt1
+ mtdcr memcfga,r4
+ addis r4,0,0x8080 // set DC_EN=1
+ ori r4,r4,0x0000
+ mtdcr memcfgd,r4
+
+ //-------------------------------------------------------------------
+ // Delay to ensure 10msec have elapsed since reset. This is
+ // required for the MPC952 to stabalize. Assume worst
+ // case that the core is running 200Mhz:
+ // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
+ // This delay should occur before accessing SDRAM.
+ //-------------------------------------------------------------------
+ addis r3,0,0x001E
+ ori r3,r3,0x8480 // ensure 10msec have passed since reset
+ mtctr r3
+..spinlp3:
+ bdnz ..spinlp3 // spin loop
+
+ mtlr r31 // restore lr
+ blr
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
+ board/cpci405/init.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
static uchar read_byte (void);
static void write_byte (uchar byte);
-void eeprom_init (void);
-void eeprom_read (unsigned offset, uchar *buffer, unsigned cnt);
-void eeprom_write (unsigned offset, uchar *buffer, unsigned cnt);
-
/*-----------------------------------------------------------------------
* START: High -> Low on SDA while SCL is High
*/
blk_num = (offset + i) >> 8;
blk_off = (offset + i) & 0xFF;
+#ifndef CONFIG_I2C_X
write_addr (blk_num);
write_byte (blk_off);
send_start ();
read_addr (blk_num);
+#else
+ write_addr (0); /* assume addr selectors hardwired to 0 */
+ write_byte (blk_num); /* upper address octet */
+ write_byte (blk_off); /* lower address octet */
+ send_start ();
+ read_addr (0); /* assume addr selectors hardwired to 0 */
+#endif /* CONFIG_I2C_X */
*buffer++ = read_byte();
send_stop ();
}
blk_num = (offset + i) >> 8;
blk_off = (offset + i) & 0xFF;
+#ifndef CONFIG_I2C_X
write_addr (blk_num);
write_byte (blk_off);
+#else
+ write_addr (0); /* assume addr selectors hardwired to 0 */
+ write_byte (blk_num); /* upper address octet */
+ write_byte (blk_off); /* lower address octet */
+#endif /* CONFIG_I2C_X */
write_byte (*buffer++);
send_stop ();
}
/* Pointer to initial global data area */
init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
+#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || defined(CONFIG_CANBT)
+ board_pre_init(); /* very early board init code (fpga boot, etc.) */
+#endif
+
#if defined(CONFIG_8260)
get_8260_clks();
*/
init_timebase ();
- idata->env_addr = env_init();
+ env_init (idata);
i = getenv_r ("baudrate", tmp, sizeof(tmp));
baudrate = (i > 0) ? (int)simple_strtoul(tmp, NULL, 10) : CONFIG_BAUDRATE;
void env_relocate (ulong offset)
{
init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
-#ifndef CFG_ENV_IS_IN_EEPROM
- uchar *datap = (uchar *)(idata->env_addr + offset);
-#endif
#if !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_IS_IN_NVRAM)
/*
get_env_char = get_env_char_memory;
get_env_addr = get_env_addr_memory;
- if (
-#ifdef CFG_ENV_IS_IN_EEPROM
- idata->env_addr == 0
-#else
- datap == &default_environment[0]
-#endif
- ) {
+ if (idata->env_valid == 0) {
/*
- * We should check here that the default environment
- * does not overflow the buffer.
+ * TODO: We should check here that the
+ * default environment does not overflow the buffer.
*/
printf ("*** Warning - bad CRC, using default environment\n\n");
memset (env_ptr, 0, sizeof(env_t));
memcpy (env_ptr->data,
default_environment,
sizeof(default_environment));
+ idata->env_valid = 1;
}
#if !defined(ENV_IS_EMBEDDED)
else {
static uchar get_env_char_memory (int index)
{
init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
- uchar *datap = (uchar *)idata->env_addr;
- return (datap[index]);
+ if (idata->env_valid) {
+ return ( *((uchar *)(idata->env_addr + index)) );
+ } else {
+ return ( default_environment[index] );
+ }
}
static uchar *get_env_addr_memory(int index)
{
init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
- uchar *datap = (uchar *)idata->env_addr;
-
- return (&datap[index]);
+
+ if (idata->env_valid) {
+ return ( ((uchar *)(idata->env_addr + index)) );
+ } else {
+ return (&default_environment[index]);
+ }
}
#ifdef CFG_ENV_IS_IN_EEPROM
for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
int val;
- for (nxt=i; get_env_char(nxt) != '\0'; ++nxt)
- ;
+ for (nxt=i; get_env_char(nxt) != '\0'; ++nxt) {
+ if (nxt >= CFG_ENV_SIZE) {
+ return (NULL);
+ }
+ }
if ((val=envmatch(name, i)) < 0)
continue;
return (get_env_addr(val));
int getenv_r (uchar *name, uchar *buf, unsigned len)
{
int i, nxt;
+ init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
+ uchar (*my_get_env_char)(int);
- for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
+ /* Use default environment and memory routine in case of bad CRC */
+ if (idata->env_valid) {
+ my_get_env_char = get_env_char;
+ } else {
+ my_get_env_char = get_env_char_memory;
+ }
+
+ for (i=0; my_get_env_char(i) != '\0'; i=nxt+1) {
int val, n;
- for (nxt=i; get_env_char(nxt) != '\0'; ++nxt)
- ;
+ for (nxt=i; my_get_env_char(nxt) != '\0'; ++nxt) {
+ if (nxt >= CFG_ENV_SIZE) {
+ return (-1);
+ }
+ }
if ((val=envmatch(name, i)) < 0)
continue;
/* found; copy out */
n = 0;
- while ((len > n++) && (*buf++ = get_env_char(val++)) != '\0')
+ while ((len > n++) && (*buf++ = my_get_env_char(val++)) != '\0')
;
if (len == n)
*buf = '\0';
* We are still running from ROM, so data use is limited
*/
#ifndef CFG_ENV_IS_IN_EEPROM
-ulong env_init(void)
+void env_init(init_data_t *idata)
{
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
- return ((ulong)&(env_ptr->data));
+ idata->env_addr = (ulong)&(env_ptr->data);
+ idata->env_valid = 1;
} else {
- return ((ulong)&default_environment);
+ idata->env_addr = (ulong)&default_environment;
+ idata->env_valid = 0;
}
}
#else /* CFG_ENV_IS_IN_EEPROM */
/*
* Use a (moderately small) buffer on the stack
*/
-ulong env_init(void)
+void env_init(init_data_t *idata)
{
ulong crc, len, new;
unsigned off;
len -= n;
off += n;
}
+
+
if (crc == new) {
- return (offsetof(env_t,data));
+ idata->env_addr = offsetof(env_t,data);
+ idata->env_valid = 1;
} else {
- return (0);
+ idata->env_addr = 0;
+ idata->env_valid = 0;
}
}
#endif /* CFG_ENV_IS_IN_EEPROM */
* BRO = Reject broadcast packets
* PROMISCOUS = Catch all packetsregardless of dest. MAC adress
*/
- immr->im_cpm.cp_scc[SCC_ENET].scc_pmsr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22
+ immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22
/* | SCC_PMSR_BRO | SCC_PMSR_PRO */);
/*
/* Set up the baud rate generator.
* See 8xx_io/commproc.c for details.
*
- * Wire BRG1 to SMC1 and BRG2 to SMC2.
+ * Wire BRG1 to SMCx
*/
cp->cp_simode = 0x10000000;
-#if defined(CONFIG_8xx_CONS_SMC1)
- cp->cp_brgc1 = /* Console on SMC1 */
-#else
- cp->cp_brgc2 = /* Console on SMC2 */
-#endif
+ cp->cp_brgc1 =
(((cpu_clock / 16 / baudrate)-1) << 1) | CPM_BRG_EN;
}
*/
im->im_siu_conf.sc_sdcr = 1;
+#if (SCC_INDEX < 2) || !defined(CONFIG_IP860)
+ /*
+ * Standard configuration for SCC's in on Part A
+ */
ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
+#else
+ /*
+ * The IP860 has SCC3 and SCC4 on Port D
+ */
+ ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
+#endif
/* Allocate space for two buffer descriptors in the DP ram.
*/
* Set up the baud rate generator.
* See 8xx_io/commproc.c for details.
*
- * Wire BRGn to SCCn
+ * Wire BRG1 to SCCn
*/
/* Set up the baud rate generator.
sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
-#if defined(CONFIG_8xx_CONS_SCC1)
- cp->cp_sicr |= (SICR_RCLK_SCC1_BRG1 | SICR_TCLK_SCC1_BRG1);
- cp->cp_brgc1 =
- ((((cpu_clock / 16) / baudrate)-1) << 1) | CPM_BRG_EN;
-#elif defined(CONFIG_8xx_CONS_SCC2)
- cp->cp_sicr |= (SICR_RCLK_SCC2_BRG2 | SICR_TCLK_SCC2_BRG2);
- cp->cp_brgc2 =
- ((((cpu_clock / 16) / baudrate)-1) << 1) | CPM_BRG_EN;
-#elif defined(CONFIG_8xx_CONS_SCC3)
- cp->cp_sicr |= (SICR_RCLK_SCC3_BRG3 | SICR_TCLK_SCC3_BRG3);
- cp->cp_brgc3 =
- ((((cpu_clock / 16) / baudrate)-1) << 1) | CPM_BRG_EN;
-#elif defined(CONFIG_8xx_CONS_SCC4)
- cp->cp_sicr |= (SICR_RCLK_SCC4_BRG4 | SICR_TCLK_SCC4_BRG4);
- cp->cp_brgc4 =
- ((((cpu_clock / 16) / baudrate)-1) << 1) | CPM_BRG_EN;
-#endif
+ serial_setbrg (cpu_clock, baudrate);
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
- sp->scc_pmsr |= SCU_PMSR_CL;
+ sp->scc_psmr |= SCU_PMSR_CL;
/* Mask all interrupts and remove anything pending.
*/
sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
+void
+serial_setbrg (ulong cpu_clock, int baudrate)
+{
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile cpm8xx_t *cp = &(im->im_cpm);
+
+ /* Set up the baud rate generator.
+ * See 8xx_io/commproc.c for details.
+ *
+ * Wire BRG1 to SCCx
+ */
+
+ cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
+ /* no |= needed, since BRG1 is 000 */
+
+ cp->cp_brgc1 =
+ (((cpu_clock / 16 / baudrate)-1) << 1) | CPM_BRG_EN;
+}
void
serial_putc(const char c)
#include <405gp_pci.h>
#include <asm/processor.h>
+
+void pciinfo(int bus_no);
+
#ifdef CONFIG_PPC405GP
#ifdef CONFIG_PCI_PNP
#include <ppc4xx.h>
-
/* ------------------------------------------------------------------------- */
int checkcpu(long clock)
uint pvr = get_pvr();
char buf[32];
-#ifdef CONFIG_PPC405GP
+#ifdef CONFIG_PPC405
PPC405_SYS_INFO sys_info;
get_sys_info(&sys_info);
+#if CONFIG_PPC405GP
printf("IBM PowerPC 405GP Rev. ");
+#endif
+#if CONFIG_PPC405CR
+ printf("IBM PowerPC 405CR Rev. ");
+#endif
switch (pvr)
{
case PVR_405GP_RB:
case PVR_405GP_RD:
putc('D');
break;
+ case PVR_405CR_RA:
+ putc('A');
+ break;
+ case PVR_405CR_RB:
+ putc('B');
+ break;
default:
printf("? (PVR=%08x)", pvr);
break;
sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
+#if CONFIG_PPC405GP
if (mfdcr(strap) & PSR_PCI_ASYNC_EN)
printf(" PCI async ext clock used, ");
else
printf("internal PCI arbiter enabled\n");
else
printf("external PCI arbiter enabled\n");
+#endif
switch (pvr)
{
case PVR_405GP_RB:
case PVR_405GP_RC:
case PVR_405GP_RD:
+ case PVR_405CR_RA:
+ case PVR_405CR_RB:
printf(" 16 kB I-Cache 8 kB D-Cache");
break;
}
-#endif
+#endif /* CONFIG_PPC405 */
#ifdef CONFIG_IOP480
printf("PLX IOP480 (PVR=%08x)", pvr);
*/
unsigned long get_tbclk (void)
{
-#ifdef CONFIG_PPC405GP
+#ifdef CONFIG_PPC405
PPC405_SYS_INFO sys_info;
get_sys_info(&sys_info);
return (sys_info.freqProcessor);
-#endif /* CONFIG_PPC405GP */
+#endif /* CONFIG_PPC405 */
#ifdef CONFIG_IOP480
return (66000000);
void
cpu_init_r (bd_t *bd)
{
+#ifdef CONFIG_PPC405GP
unsigned long reg;
/*
reg = reg << 8;
reg |= bd->bi_enetaddr[5];
out32 (EMAC_IAL, reg);
-
+#endif /* CONFIG_PPC405GP */
}
+++ /dev/null
- 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
- 0x63,0x70,0x63,0x69,0x34,0x30,0x35,0x32,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
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- 0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbc,0xf8,0xbe,0xef,0x9b,0xe7,0xfb,0xff,0x4f,0xff,
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- 0xff,0xff,0xbf,0xff,0xff,0xff,0x7f,0xff,0xdf,0xff,0xff,0xff,0xff,0xe8,0xbd,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xc5,0x7f,0xfb,
- 0xfe,0xff,0xff,0xef,0xf3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xcb,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x07,0xff,0xff,
- 0xff,0xb7,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x4f,0xff,0xf7,
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- 0xfb,0xfe,0xff,0xbf,0xef,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xfc,0xbf,0xfe,0x7d,
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- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x1b,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd4,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xb3,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf1,0xff,0xbb,0xfe,0xff,0xbf,0xef,0xfb,
- 0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0x7e,0xb6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xf6,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd0,0xff,0xff,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,
- 0xff,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe1,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x57,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xf2,0x3f,0xff,0xeb,0xfa,0xfe,0xbf,0xaf,0xeb,0xfe,
- 0xaf,0xaf,0xeb,0x7a,0xfe,0xbf,0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xac,0x7f,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xa9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xb9,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xfe,0x17,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xfe,0xe7,0xff,0xff,0xfe,0x7f,0xff,0xff,0xff,0xe7,0xef,
- 0xff,0xff,0xff,0xff,0xff,0xfb,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xfb,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xf3,0x7f,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0x7f,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xf8,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xc9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xa3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0x17,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0x8b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xf5,0x5a,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0x78,0x3d,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xd6,0xd7,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0x3f,0x64,0xff,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xbd,0xb7,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xfd,0xd1,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xfe,0x07,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xa7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xf8,0x0f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xf9,0x1f,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xfb,0xfe,0xff,0xbf,
- 0xef,0xfb,0xff,0xaa,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xea,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0x5d,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xfe,0xff,0xab,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0x67,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xfc,0x4f,0xff,0xff,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xf9,0xfe,0x7f,0x9f,
- 0xe7,0xf9,0xff,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xfd,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xf5,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xea,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xf1,0xff,0x7f,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xbb,0xff,0xfe,0x9f,0xaf,0xeb,0xfa,0xfe,0xbf,0xeb,0xfa,0xfe,0xaf,0xaf,
- 0xeb,0x7d,0x57,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xfe,0x67,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,
- 0xff,0xfa,0x9f,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xfb,0xbd,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xf6,0x3f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xf8,0x6f,0xdf,0x7d,0xff,0xee,0xff,0xbf,0xfe,0xfe,0xff,0xff,0xdf,0xff,0xff,
- 0xff,0xe8,0xff,0xff,0xff,0xff,0x3f,0xd7,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xe2,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0x83,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xaf,0xf7,0xfe,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xfe,0x9f,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xff,
- 0xb9,0x3f,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,
- 0xeb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xfe,
- 0xe0,0xbf,0xff,0xff,0xff,0xff,0xff,0xd7,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0x11,0xaf,0xff,0xff,0xff,0xff,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd5,
- 0x92,0x5f,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,
- 0xf6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
- 0x87,0xff,0x7f,0xff,0xfa,0xfe,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
- 0xd3,0xf8,0xff,0xff,0xf5,0x7d,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xde,
- 0xb7,0xff,0xff,0xff,0xeb,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe9,
- 0x7f,0xff,0xff,0xff,0xd7,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfa,
- 0x7f,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf1,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,
- 0xff,0xfb,0xf6,0xff,0xbf,0xef,0xfb,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xfe,0xe7,
- 0xff,0xff,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf6,0x2b,
- 0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0x1f,
- 0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xff,0xe8,0xbf,
- 0xff,0xff,0xb7,0xff,0xff,0xff,0xff,0xff,0xf2,0x7f,0xff,0xff,0xff,0xff,0xf2,0x3f,
- 0xdf,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xf5,0xff,0xff,0xff,0xff,0xff,0xe0,0xff,
- 0xff,0xe0,0xfa,0x7e,0x9f,0xa7,0xed,0xff,0x8b,0xe7,0xf9,0xfe,0x7f,0x9f,0xd1,0xff,
- 0xff,0xff,0x77,0xfd,0xff,0x7f,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,
- 0xff,0xf3,0xff,0xff,0x7f,0xff,0xff,0xff,0x6f,0xff,0xff,0xff,0xff,0xff,0xf3,0xff,
- 0xff,0x1d,0xf7,0xfd,0xff,0x7f,0x5f,0xfe,0xdf,0xff,0xff,0xff,0xff,0xff,0x8e,0xff,
- 0xfe,0x0f,0xaf,0xf1,0xfe,0xff,0xff,0xf7,0xbf,0xff,0xff,0xff,0xff,0xfc,0xdf,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x3f,0xff,
- 0xe9,0xfa,0x7e,0x9f,0xa7,0xeb,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,0xbf,0xf7,0x5f,0xff,
- 0xff,0xff,0x7f,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xec,0x7f,0xff,
- 0xf7,0xff,0xff,0xff,0xf7,0xff,0x7f,0xfe,0xff,0xff,0xff,0xff,0xff,0x8d,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb1,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xf9,0xf7,0xaf,0xff,0xff,0xff,0xff,0xfe,0x87,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xf7,0xdf,0x6f,0xff,0xff,0xff,0xff,0xff,0xa7,0xfd,0xff,
- 0xfd,0xfe,0xff,0xf7,0x7f,0xef,0xef,0xff,0xfd,0xff,0xff,0xff,0xf9,0x5f,0xff,0xff,
- 0xff,0xf1,0xdf,0xff,0xff,0xdf,0xbf,0xff,0xff,0xff,0xff,0xff,0xf9,0xbf,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xbf,0xf7,0xff,0xff,0xff,0xff,0xf7,0xff,0x7f,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd5,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xbf,0xfd,0xff,0xff,0xb3,0xff,0xff,0xbf,
- 0xff,0xff,0xff,0xff,0xff,0x3f,0xff,0xff,0xff,0xfd,0xff,0xff,0x97,0xff,0xff,0xbf,
- 0xff,0xff,0xff,0xff,0xfe,0xff,0xfb,0xff,0xff,0xbf,0xff,0xff,0xea,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x5b,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0xff,0x5e,0xa7,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x2b,0xfe,0xfa,0x2d,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xd7,0x9f,0x7a,0x7b,0xff,0xff,0xff,
- 0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xef,0xdf,0xb8,0x3f,0xff,0xff,0xff,
- 0x57,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x77,0x7d,0xf3,0x7f,0xff,0xff,0xfe,
- 0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xbf,0xfe,0x13,0xff,0xff,0xff,0xfd,
- 0x7f,0xff,0xff,0xff,0xfa,0xff,0xff,0xff,0xfd,0x7f,0xfe,0x8f,0xfb,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xed,0xff,0xff,0xff,0xff,0xef,0xfb,0x17,0xfa,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xe7,0xff,0xff,0xff,0xff,0xeb,0xfe,0x1f,0xef,0xbf,0xef,0xdb,
- 0xfe,0xfd,0xbd,0x7b,0xfe,0xff,0xbf,0xef,0xfb,0x67,0xed,0x7f,0xff,0xff,0xfd,0xbf,
- 0xff,0xf3,0xfe,0xff,0xff,0xff,0xff,0xff,0xbf,0x6f,0x72,0xbf,0xff,0xff,0xfb,0xff,
- 0xff,0xbf,0xef,0xff,0xff,0xff,0xff,0xfe,0xff,0x7f,0xfd,0xff,0xff,0xff,0xff,0xdf,
- 0xff,0xfd,0xff,0x5f,0xff,0xff,0xff,0xff,0xdf,0xff,0xcb,0xff,0xff,0xff,0xfe,0xdf,
- 0xff,0xed,0xf6,0x9f,0xff,0xff,0xff,0xfe,0xdf,0xff,0x33,0xff,0xff,0xff,0xff,0x7f,
- 0xff,0xf7,0xfd,0x7f,0xff,0xff,0xff,0xfd,0x7f,0xff,0x6f,0xfb,0xfe,0x9f,0xa3,0xe5,
- 0xfb,0x3e,0xdb,0xf1,0xfe,0x7f,0x9f,0xe2,0xf9,0xfc,0x5f,0xff,0xff,0xff,0xfd,0xcf,
- 0xff,0xdd,0xf4,0x7f,0xff,0xff,0xff,0xfd,0xff,0xfb,0x3f,0xff,0xff,0x7f,0xef,0xf7,
- 0xfe,0xff,0xeb,0xd7,0xff,0xff,0xff,0xef,0xff,0xfa,0x3f,0xff,0xf5,0xfd,0x77,0xcf,
- 0xd7,0x7d,0xd7,0xef,0xff,0xff,0xff,0xd7,0xff,0xe8,0xff,0xff,0xe1,0xfa,0xbe,0xff,
- 0xbb,0xef,0xa7,0x7f,0xff,0xff,0xff,0xaf,0xff,0xec,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0x93,0xff,0xfe,0xbf,0xaf,0xeb,0xfa,
- 0xbe,0xbf,0xeb,0x7a,0x7e,0xbf,0xad,0xeb,0xff,0xe5,0xff,0x7f,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x07,0xbf,0xff,0xff,0xef,0xff,0xff,
- 0xff,0xf7,0xbf,0xfe,0xff,0xff,0xff,0xff,0xfa,0x5f,0x7f,0xff,0xff,0xff,0xef,0xff,
- 0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xf7,0xa3,0xff,0xff,0xeb,0xff,0xff,0xff,0xe0,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xdf,0x5f,0x7f,0xff,0xff,0xff,0xff,0xff,0xfc,0x7f,0xd6,0xff,0xff,0xfe,0xdf,0xbf,
- 0xfe,0xff,0xff,0xff,0xef,0xfe,0xff,0xff,0x99,0xff,0xf1,0xfb,0xff,0xff,0xff,0xff,
- 0xfd,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xc3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xe3,0xff,0xfb,0xff,0xff,0xff,0xff,0xf7,0xa7,0xdf,0xff,0xdf,0xff,0xfe,0xff,0xbf,
- 0xd4,0x7f,0xff,0xff,0xff,0xff,0xcf,0xff,0xcf,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xaf,0x77,0xff,0xff,0xff,0xff,0xff,0xfe,0x9f,0xff,0xff,0x7f,0xff,0xff,0xff,0x5f,
- 0xef,0xff,0xfb,0xdf,0xff,0xef,0xff,0xf9,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,
- 0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xfd,0x7e,0xff,0xff,0xfe,0xff,0xff,0xee,0xfb,
- 0xbf,0xff,0xfd,0xfb,0xff,0xff,0xff,0xe2,0xbf,0xff,0xff,0xff,0xfe,0x7d,0xff,0xf5,
- 0xff,0xef,0xfb,0xdf,0xfd,0x33,0xff,0x65,0xaf,0xff,0xff,0xff,0xfe,0xbf,0xff,0xe7,
- 0x3f,0xdf,0xf7,0xff,0xf3,0x3f,0xf5,0xc2,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xbc,0xff,0x4b,0xff,0xfe,0xaf,0xef,0x86,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
- 0xff,0xfe,0xd7,0xff,0xfd,0xf3,0xff,0xa7,0xff,0x2f,0xff,0xff,0xff,0xff,0xff,0xfe,
- 0xdc,0xf6,0xbd,0xff,0xfa,0xf5,0xfb,0x53,0xf8,0x57,0xff,0xff,0xff,0xff,0xff,0xf7,
- 0x51,0xef,0x77,0xff,0xf7,0x7b,0xdc,0xb6,0xfe,0xbf,0xff,0xff,0xff,0xe7,0xff,0xfb,
- 0xff,0xfe,0xaf,0xff,0xeb,0x6f,0xbb,0x7f,0xfd,0x7a,0xff,0xff,0xff,0xeb,0xff,0xdd,
- 0xff,0xfd,0x7f,0xff,0xdf,0xff,0xe8,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
- 0xff,0xbf,0x67,0xfb,0xff,0xff,0xbd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe7,
- 0xff,0xee,0x7f,0xfa,0xfe,0x7f,0xa1,0xff,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xff,0x9f,
- 0x6f,0xd8,0xfe,0xfb,0xb7,0x7e,0x37,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,
- 0xf7,0x3f,0xff,0xff,0xf6,0xf6,0x4b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,
- 0xfe,0xff,0xff,0xff,0xef,0xfc,0x5f,0xff,0xff,0xff,0xf5,0xff,0xff,0xdf,0xfe,0x7d,
- 0x7f,0x47,0xd7,0xf5,0xff,0xf9,0x37,0xff,0xff,0xff,0xe9,0xff,0xff,0x9f,0xfe,0xfa,
- 0xbc,0x8f,0xa7,0xc9,0xff,0xf6,0x3f,0xff,0xff,0xff,0xd7,0xff,0xff,0x7b,0xff,0x7d,
- 0xed,0x5f,0xff,0xd7,0xff,0xf6,0xff,0xff,0xe1,0xfa,0x2e,0x1f,0xa6,0xe9,0xf7,0x0f,
- 0xe2,0xf9,0xfe,0x2f,0x9f,0xcd,0x7f,0xfe,0x6b,0xff,0xfe,0xbf,0xfd,0xdf,0xee,0x97,
- 0xf4,0xfd,0x7f,0xff,0xff,0xfb,0xff,0xff,0xa7,0xfb,0xfe,0x7f,0xbb,0xef,0xdf,0x2f,
- 0xeb,0xfa,0xff,0xff,0xff,0x27,0xff,0xff,0xdf,0xd7,0xf5,0xfd,0x77,0xdb,0xff,0xff,
- 0xf3,0xff,0xfd,0x7f,0xff,0xcf,0x7f,0xf6,0xff,0xbf,0xe7,0xdf,0xee,0xff,0xdf,0xf7,
- 0xad,0xff,0xfa,0xff,0xfe,0x4e,0xff,0xfe,0xff,0xbf,0xef,0xff,0xff,0xff,0xef,0xbf,
- 0x2f,0xff,0xf7,0xff,0xf2,0x3b,0xff,0xeb,0xfa,0xfe,0xbf,0xad,0xeb,0xde,0xaf,0xa6,
- 0xea,0xfa,0xee,0xbb,0xf5,0x57,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,
- 0x3f,0xff,0xff,0xff,0xae,0x7f,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xfd,
- 0xff,0xef,0xff,0x7f,0x81,0xff,0xff,0xff,0xff,0xff,0xfd,0xef,0xfc,0xff,0xff,0xfd,
- 0xff,0xff,0xff,0xff,0xa1,0xfc,0xff,0xef,0xfe,0xff,0x7f,0xff,0xff,0xff,0xef,0x63,
- 0xff,0xfe,0xb7,0xde,0x87,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xf7,0xef,0x7f,0xef,
- 0xff,0xff,0x7f,0xfe,0xe7,0xff,0xff,0xff,0x7f,0xff,0xfb,0xce,0xef,0xff,0xb7,0xf7,
- 0xfb,0x7b,0xdf,0xf8,0x1f,0xfd,0xff,0xfb,0xdf,0xff,0xf7,0x6f,0xcf,0xfc,0x7f,0xff,
- 0xcf,0xff,0xff,0xfa,0x3f,0xef,0xff,0xff,0xff,0xff,0xfe,0xff,0x9f,0xff,0xbf,0xfe,
- 0xef,0xff,0xff,0xfb,0x7f,0xff,0xff,0xff,0xc7,0xfb,0xfc,0x7f,0x7f,0xff,0xff,0xfa,
- 0xff,0x8f,0xff,0xf8,0xff,0xff,0xe7,0xfb,0xef,0xf7,0xdf,0x6e,0xff,0xff,0xef,0xff,
- 0xff,0xef,0xff,0xf5,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xfd,
- 0x7f,0xbb,0xf7,0xdb,0xff,0xff,0xff,0xff,0xef,0xff,0xfe,0xff,0xef,0xff,0xff,0xff,
- 0xbf,0xff,0xff,0x37,0xff,0xff,0xff,0xff,0xff,0xf7,0xfe,0xff,0xf7,0xf7,0xff,0xff,
- 0xff,0xff,0xff,0x0f,0xbf,0xfb,0xef,0xfc,0xbe,0xdf,0xbf,0xff,0xff,0xff,0xff,0xef,
- 0x7f,0x7f,0x7c,0xda,0xf9,0xff,0xdf,0xfb,0xfd,0xff,0xb7,0xf7,0xfd,0x9f,0xef,0xfd,
- 0xfe,0xdd,0xfc,0x8f,0xff,0xff,0xff,0xfc,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,0xbf,
- 0xec,0xff,0xdb,0x6b,0xff,0xff,0xff,0xfb,0xf2,0xfc,0x7f,0xcf,0xaf,0xff,0xff,0x1f,
- 0xdb,0xfd,0xec,0xf7,0xff,0xff,0xfc,0xaf,0xfb,0xfe,0xff,0xef,0xff,0xff,0xfe,0xff,
- 0xbf,0xfb,0x55,0xbf,0xff,0xff,0xff,0x5f,0xdf,0xf7,0xff,0x7f,0xff,0xff,0xef,0x7f,
- 0x7e,0x7f,0xeb,0xff,0xff,0xff,0xff,0xff,0xef,0xeb,0xb7,0xb3,0x2d,0xff,0xea,0xfc,
- 0xff,0xfe,0x74,0xdf,0xff,0xff,0xff,0xdf,0x77,0x95,0xfd,0xd6,0x57,0xff,0xf5,0x75,
- 0xdf,0xfe,0x0d,0xff,0xff,0xff,0xda,0xff,0xbe,0xaf,0xfe,0xfe,0xbf,0xff,0xeb,0xfb,
- 0xff,0xff,0xdf,0xff,0xff,0xff,0x95,0xfd,0xf3,0x5f,0xf7,0x4d,0x5f,0xff,0xd7,0xf7,
- 0xff,0xcb,0x3f,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xfd,0xff,0x7f,0xff,0xff,0xff,
- 0xff,0xe0,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xfe,0x7f,0xff,0xfe,0xff,
- 0xff,0xf8,0x7f,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xe7,0xf9,0xfe,0xfd,0xbb,0xef,
- 0x5f,0x89,0xbf,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xdb,0xff,0xff,
- 0xbf,0xe3,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xef,0xfb,0xff,0xbf,0xff,0xfe,
- 0xfd,0xc5,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xbf,0xef,0xff,0xf5,0xff,0xff,
- 0xff,0x4f,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xbf,0xef,0xff,0xe9,0xff,0xff,
- 0xfe,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xdf,0xff,0xff,
- 0xf1,0xbf,0xff,0xfe,0x7e,0x1f,0xa7,0xe1,0xf8,0x7f,0xa7,0xf1,0xfa,0x3f,0x9f,0x87,
- 0xf3,0x7f,0xff,0xff,0xe7,0xff,0xee,0x79,0xbf,0xf9,0xff,0xeb,0xbf,0xdf,0xff,0x6f,
- 0xe2,0xff,0xff,0xff,0xfb,0x7f,0x9f,0xb6,0x6d,0xff,0xdf,0xe7,0xe8,0xff,0xff,0x9f,
- 0xe1,0xff,0xff,0xff,0xf9,0xfd,0x7f,0x97,0xe6,0xfd,0x3f,0xde,0xf7,0x7f,0xfe,0x7f,
- 0x53,0xdf,0xff,0xff,0x61,0xfd,0xf6,0xb9,0x87,0xf0,0xfc,0xfd,0x93,0xff,0xff,0xff,
- 0x72,0xff,0xff,0xff,0xff,0xff,0xfb,0xdf,0xff,0xff,0xff,0xfd,0xff,0xfc,0xbf,0xfe,
- 0xce,0x7f,0xfa,0xbe,0xbf,0xaf,0xeb,0xda,0x77,0xaf,0xeb,0x7a,0xfe,0xbf,0xaf,0xff,
- 0xd7,0xff,0xff,0x7f,0xff,0xb7,0xf7,0xff,0xfc,0x7f,0x1b,0xcf,0xff,0xfb,0xff,0xcc,
- 0x1f,0xff,0xff,0xff,0xff,0xdf,0xfb,0xfd,0xef,0x7b,0xff,0xff,0xff,0xff,0x7f,0xea,
- 0x7f,0xff,0xff,0xff,0xff,0xff,0xf7,0xfd,0x2d,0xfb,0xfd,0x7f,0xff,0xff,0xfb,0xf0,
- 0xf7,0xff,0xff,0xdf,0xff,0xff,0xf2,0xbd,0x7f,0xff,0xff,0x7e,0x9f,0xff,0xff,0x88,
- 0xdf,0xff,0xff,0xff,0xff,0xff,0xfe,0xfd,0xf7,0xff,0xff,0xff,0x7f,0xff,0xff,0xf9,
- 0xff,0xff,0xbf,0xff,0xfa,0xef,0xe3,0xfb,0xff,0xff,0xff,0xbb,0xff,0xff,0xfe,0x73,
- 0xff,0xff,0xff,0x7f,0xff,0x3f,0xdf,0xf5,0xfb,0x7f,0xff,0xff,0xff,0xff,0xfe,0x6f,
- 0xff,0xfe,0xff,0xff,0xfe,0xf5,0xbd,0xe6,0xbe,0xfe,0xff,0xff,0xff,0xff,0xdd,0x0f,
- 0x7f,0xff,0x7f,0xff,0xff,0xbf,0xfd,0xdf,0xff,0xfd,0xff,0xfd,0xff,0xff,0xfe,0xbf,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xf7,0xff,0xff,0xff,0xff,0x9f,0xf3,0x7f,
- 0xff,0xff,0xff,0xfe,0xf5,0xff,0x77,0xbf,0xfd,0xff,0x7f,0xf7,0x7f,0xff,0xf2,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xfd,0xd7,0xfd,0xb2,0xfe,0xfd,0xff,0xff,0xff,0xd5,0xff,
- 0xff,0xef,0xff,0xff,0xff,0xff,0xbf,0xff,0xef,0xf5,0xff,0xff,0xff,0xdd,0xd2,0xff,
- 0xff,0xff,0xff,0xff,0xbe,0x6f,0xff,0xf7,0xff,0xff,0x7f,0xff,0xff,0xff,0xc6,0xbf,
- 0xff,0xff,0xff,0xff,0x3f,0xdf,0xff,0xff,0xff,0xcf,0xff,0xff,0xff,0xdf,0x89,0x7f,
- 0xff,0xff,0xff,0xe6,0xb9,0xaf,0xff,0xf3,0xf9,0xff,0xff,0xff,0xe7,0xbd,0x5b,0xff,
- 0xff,0xff,0xff,0xe5,0x73,0x5e,0x7f,0xe7,0xf3,0xff,0xff,0xff,0xe7,0xf9,0x9f,0xf5,
- 0xff,0xff,0xff,0xfa,0xec,0xbf,0xef,0xb6,0x75,0xbb,0x7f,0xff,0xfb,0xea,0x6f,0xff,
- 0xff,0xff,0xff,0xf5,0x7d,0x5f,0xfd,0xff,0xd9,0xff,0xff,0xff,0xff,0x6a,0x7f,0xff,
- 0xff,0xff,0xff,0xeb,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf9,0xff,0xff,
- 0xff,0xff,0xfe,0x97,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x99,0xff,0xff,
- 0xff,0xff,0xff,0xfe,0xdf,0xbf,0xfb,0xf6,0xdf,0xb7,0xff,0xff,0xfe,0xf7,0xff,0xff,
- 0xff,0xff,0xff,0xfe,0xff,0x8f,0xda,0xff,0xfc,0xff,0xff,0xff,0xff,0x47,0xff,0xef,
- 0xfb,0xfe,0xf5,0xb3,0x6d,0xfe,0xfb,0xbf,0x6f,0xfb,0xfe,0xf5,0xf8,0x9f,0xff,0xff,
- 0xff,0xff,0xfb,0xf6,0xff,0xff,0xfb,0xfc,0xff,0xff,0xff,0xfb,0xfd,0x2f,0xff,0xff,
- 0xff,0xff,0xef,0xfb,0xff,0xfe,0xbf,0xfb,0xff,0xff,0xff,0xdf,0xd5,0x7f,0xff,0xff,
- 0xff,0xff,0xf5,0xfd,0x7f,0xff,0xe4,0xfd,0x7f,0xff,0xff,0xff,0xe8,0xff,0xff,0xff,
- 0xff,0xff,0xe9,0xfa,0x77,0xfb,0xc9,0xda,0xaf,0xff,0xff,0xff,0xe0,0xff,0xff,0xff,
- 0xff,0xff,0xd7,0xfd,0xef,0x5d,0xf7,0xb5,0xff,0xff,0xff,0xff,0x3b,0xff,0xff,0xe7,
- 0xf9,0xfd,0x2f,0x8b,0xe6,0xbe,0x2f,0xab,0xe7,0xf9,0xfe,0xef,0x67,0xff,0xff,0xff,
- 0xff,0x9f,0xdf,0xd7,0xff,0xbf,0x5f,0x5f,0xdf,0xff,0xfd,0xff,0x8f,0xff,0xff,0xff,
- 0xff,0xf4,0xbf,0x2f,0xff,0xfe,0xbf,0x7f,0xff,0xff,0xfd,0xfd,0xdf,0xff,0xff,0xff,
- 0xff,0xf1,0x7e,0x5f,0xee,0xfd,0x7d,0xff,0x7f,0xff,0xf7,0xf0,0xbf,0xfd,0xff,0xff,
- 0xfd,0x9a,0xf6,0x9f,0xff,0x7a,0xff,0xf7,0xff,0xff,0xff,0x7e,0x7f,0xff,0xff,0xff,
- 0xff,0xf6,0xfd,0x3f,0xd1,0xfa,0xbf,0xff,0xff,0xff,0xfe,0xee,0xff,0xff,0xaf,0xeb,
- 0xfa,0xf6,0xbb,0x2f,0x5a,0xfe,0xbf,0xab,0xeb,0xfa,0xff,0xfd,0xff,0xff,0xff,0xff,
- 0xfd,0xdf,0xef,0xff,0xf7,0xf3,0xef,0xff,0xff,0xff,0xbe,0xf9,0xff,0xff,0xf7,0xff,
- 0xff,0xff,0xff,0xbd,0xdb,0x2b,0x7f,0xf7,0xfb,0xff,0xfe,0xd7,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xbd,0xe7,0xff,0xf7,0xbf,0xef,0xfb,0xff,0xfe,0x2f,0x7f,0xff,0xff,0xff,
- 0xdf,0xff,0xaf,0x76,0xe2,0xbf,0xab,0xfe,0xff,0xff,0x79,0xce,0xff,0xff,0xff,0xff,
- 0xff,0xff,0x5f,0xdf,0xff,0xb9,0xee,0xff,0x9f,0xff,0xfc,0x9d,0xff,0xff,0xfe,0x7f,
- 0xfc,0xff,0xff,0xae,0xfb,0xfe,0xbf,0xfe,0xff,0xff,0xe9,0x37,0xbf,0xff,0xef,0xff,
- 0xf7,0xdd,0x9f,0x7f,0xe7,0xfd,0xff,0xff,0xfd,0xff,0xf6,0xff,0xff,0xff,0xff,0xff,
- 0xef,0xae,0xfe,0xff,0xef,0xfb,0x7d,0xff,0xff,0xb7,0xe0,0xff,0xff,0xff,0xff,0xff,
- 0xbf,0xf3,0xed,0xff,0xef,0x7f,0xff,0xef,0xff,0xef,0xc3,0xff,0xff,0xff,0xff,0xff,
- 0xfb,0xe6,0xfb,0xff,0xdf,0xff,0x7f,0xff,0xff,0xdf,0xd7,0xff,0xff,0xff,0xff,0xfb,
- 0xca,0x77,0x7d,0x63,0xfc,0xf7,0xfd,0xff,0xff,0xff,0xef,0xfd,0xff,0xff,0xff,0xff,
- 0x7f,0x8f,0xfe,0xff,0xfd,0x47,0xfa,0xff,0xff,0xff,0x5f,0xff,0xff,0xff,0xff,0xef,
- 0xff,0xf3,0xed,0xff,0xff,0xdd,0xd7,0x7f,0xff,0xfe,0xaf,0xff,0xff,0xff,0xff,0xfb,
- 0x3f,0xff,0xef,0xfb,0xfe,0xff,0xbf,0xff,0xff,0xc5,0x6b,0xff,0xff,0xff,0xcf,0xf5,
- 0x7f,0x7f,0xff,0xf1,0xfc,0xff,0x3f,0xff,0xfd,0x7e,0xf7,0xff,0xff,0xff,0xec,0x6b,
- 0xff,0xdf,0xaf,0xeb,0xcb,0xe6,0xbf,0xff,0xfb,0xed,0xbf,0xff,0xff,0xff,0x7e,0x57,
- 0xfd,0xef,0x5f,0xd7,0xf5,0xed,0x7f,0xff,0xfd,0xc1,0xfe,0xdf,0xff,0xff,0xbf,0xae,
- 0xdd,0xc6,0xff,0x26,0xcb,0xea,0xed,0xff,0xff,0x76,0xfe,0xbf,0xff,0xfd,0xde,0x57,
- 0xfd,0x6f,0xf4,0x6e,0x95,0x65,0x6b,0xff,0xf6,0x47,0xff,0xff,0xff,0xfe,0xfa,0xbf,
- 0xff,0xfa,0xfe,0xbf,0xaf,0xeb,0xff,0xff,0x7a,0x1f,0xff,0xff,0xff,0xf7,0xfd,0x7f,
- 0xef,0xf5,0xfd,0x3f,0x5f,0xd7,0xff,0xff,0xfb,0x1f,0xef,0xff,0xff,0xff,0xff,0xef,
- 0xfb,0xff,0xff,0x6f,0xff,0xfe,0xdf,0xfd,0xf8,0x7f,0xeb,0xff,0xff,0xff,0xff,0xfb,
- 0xfe,0xfd,0xbe,0xe3,0xff,0xff,0xff,0xff,0xe2,0x7f,0xbe,0xff,0xbf,0xef,0xdb,0x56,
- 0xfd,0xef,0x99,0x56,0xfd,0xbf,0xef,0xff,0xa5,0xbf,0xff,0xff,0xff,0xff,0x3f,0xef,
- 0xdf,0xff,0x3f,0xff,0xf3,0xff,0xff,0xfd,0xe3,0xff,0xff,0xff,0xff,0xfb,0xfe,0xff,
- 0xff,0xfb,0xff,0xff,0xbf,0xff,0xff,0xff,0x97,0xff,0xff,0xff,0xff,0xff,0x5f,0xbd,
- 0xfd,0x7f,0xc7,0xdf,0xf5,0xff,0xfe,0xfe,0x2f,0xff,0xff,0xff,0xff,0xfe,0x9f,0xff,
- 0xfa,0xac,0xdf,0x77,0xe9,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xfd,0x7e,0xee,
- 0xf7,0xd9,0xbe,0x7f,0xd7,0xff,0xff,0xf5,0xbf,0xff,0xfe,0x7f,0x9f,0xe2,0xf9,0xfe,
- 0x7f,0xe6,0xf9,0xfe,0x2f,0x9f,0xe7,0xef,0x7f,0xff,0xff,0xff,0xff,0xf5,0xff,0xff,
- 0xd7,0xff,0xfd,0xff,0x5f,0xff,0xff,0xe6,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,0xff,
- 0xaf,0xff,0xff,0xff,0xbf,0xff,0xff,0xed,0xff,0x7f,0xff,0xff,0xff,0xd7,0xf7,0xfe,
- 0xff,0xff,0xf7,0xfd,0x7f,0xff,0xff,0xd3,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
- 0xf7,0xff,0xff,0xfa,0xff,0xff,0xff,0x87,0xfe,0xff,0xff,0xff,0xff,0x6f,0xf9,0xfd,
- 0xbf,0x47,0xdb,0xf6,0xff,0xff,0xfd,0x0f,0xff,0xfa,0xfe,0xbf,0xaf,0x6b,0xfa,0xf3,
- 0x8f,0x6b,0xda,0xb6,0x9f,0xaf,0xff,0xdf,0xff,0xff,0xff,0xff,0xf9,0xbf,0x7f,0xb7,
- 0xfb,0xff,0x7f,0x5f,0xef,0xef,0xf8,0x1f,0xff,0xff,0xff,0xff,0xfb,0xfd,0xdf,0xff,
- 0xff,0xff,0xff,0x7f,0xff,0xff,0x66,0x7f,0xff,0xff,0xff,0xfe,0xff,0xff,0xbf,0x7f,
- 0x7f,0xff,0xfe,0xff,0xff,0xff,0xf6,0x7f,0xff,0xff,0xfd,0xff,0xeb,0xeb,0xf7,0xaf,
- 0x67,0xff,0xf6,0xed,0xff,0xff,0xd1,0xff,0xff,0xff,0xff,0xfb,0xdb,0xfd,0xfd,0x5d,
- 0xff,0x7f,0xdf,0xbf,0xff,0xff,0xb1,0xff,0xff,0xbf,0xff,0xff,0xfe,0xf3,0xbb,0xff,
- 0xfb,0xbf,0xff,0xfb,0xff,0xfd,0x47,0xfb,0xff,0xfe,0xff,0xfd,0xff,0x5b,0xf7,0xfe,
- 0xff,0xff,0xfe,0xf7,0xff,0xff,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0x6f,0xfd,
- 0xff,0xff,0xff,0x7f,0xff,0xfc,0xdf,0x7f,0xff,0xff,0xff,0xff,0xbd,0xff,0xd2,0xff,
- 0xdf,0xff,0xd7,0xff,0xff,0xf9,0x3f,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xbb,0xff,
- 0xff,0xef,0xfb,0xff,0xff,0xfb,0x7f,0xff,0xfd,0xff,0xff,0xbf,0xff,0x7f,0xef,0xff,
- 0x7f,0xdf,0xdf,0xff,0xff,0xf2,0xff,0xef,0xff,0xfd,0xff,0xff,0xfc,0xdd,0xf3,0xff,
- 0x6f,0xff,0xff,0xff,0xff,0xa9,0xff,0xff,0xff,0xff,0xfe,0xff,0xfb,0xbf,0xff,0xff,
- 0xff,0xfd,0xff,0xff,0xff,0xd8,0xff,0xff,0xff,0xff,0xfd,0x31,0xff,0xd7,0xcf,0xf3,
- 0xff,0xff,0xff,0xff,0xfc,0xd6,0xbf,0xff,0xff,0xff,0xf3,0x77,0xff,0xac,0xbf,0xef,
- 0xff,0xff,0xff,0xff,0xd6,0x0f,0x7f,0xff,0x2b,0xff,0xfe,0xff,0xff,0xfe,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xbd,0xdb,0xff,0xff,0xd7,0xff,0xfd,0xf3,0xff,0xf7,0xff,0xff,
- 0xff,0xef,0xff,0xff,0xdd,0x3f,0xff,0xff,0xff,0xff,0xfb,0xff,0xf7,0xfb,0xd7,0xff,
- 0xff,0xf7,0xff,0xff,0xf0,0x6f,0xff,0xff,0xf7,0xff,0xf7,0x7f,0xef,0xdd,0x6f,0xff,
- 0xff,0x75,0xbf,0xfb,0x74,0x7f,0xff,0xfe,0xbf,0xff,0xef,0xfa,0xff,0xed,0xff,0xff,
- 0xff,0xff,0xff,0xf7,0x99,0xff,0xff,0xfd,0x7f,0xff,0xdf,0xf5,0xff,0x7f,0xff,0xff,
- 0xfd,0xbf,0xff,0xff,0xbb,0xfe,0xdf,0xff,0xff,0xff,0xff,0xff,0xb7,0xfb,0xff,0xff,
- 0xff,0x67,0xff,0xff,0xf7,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xfa,0xff,0xff,
- 0xff,0xff,0xff,0xff,0x07,0xfb,0xef,0xfb,0xfe,0xff,0xbf,0xef,0x9e,0xef,0xbf,0xef,
- 0xd9,0x7e,0xff,0xf9,0x9b,0xff,0xff,0xbf,0xff,0xff,0xfe,0xfd,0xff,0xff,0xff,0xff,
- 0x3f,0xff,0xff,0xd8,0xbf,0xff,0xfe,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xfe,
- 0xff,0xff,0xff,0xf2,0x7f,0xff,0xff,0xdf,0xff,0xff,0xfd,0x7f,0xf7,0xff,0xff,0xfe,
- 0xcf,0xff,0xff,0xaa,0xff,0xff,0xfe,0xdf,0xff,0xff,0xf2,0x3f,0xb7,0xff,0xff,0xff,
- 0xbf,0xff,0xff,0xec,0xff,0xff,0xff,0x7f,0xff,0xff,0xf5,0xdf,0xff,0xff,0xff,0xff,
- 0x7f,0xff,0xff,0x93,0xff,0xff,0xe3,0xe1,0xfe,0x7e,0xcb,0x97,0xfd,0x7f,0x9f,0xc6,
- 0xf9,0xfe,0x7f,0xb7,0xff,0xff,0xfd,0xcf,0xff,0xfd,0xd7,0xff,0x7f,0xff,0xff,0xfd,
- 0xff,0xff,0xfe,0xcf,0xff,0xff,0xef,0xf7,0xff,0xff,0xaf,0xdb,0xf5,0xff,0xff,0xdb,
- 0xff,0xff,0xfd,0x9f,0xfe,0xff,0xf7,0xdf,0xff,0xfd,0x5c,0x2f,0xf3,0xff,0xfe,0xb7,
- 0xff,0xff,0xf5,0x3f,0xff,0xff,0xbf,0x1f,0xff,0x7e,0xf1,0xfd,0x9f,0xff,0xfd,0xff,
- 0xff,0xfe,0xfa,0x7f,0xff,0xff,0xff,0xff,0xf2,0xff,0xff,0xff,0xff,0xff,0xff,0x2f,
- 0xff,0xff,0xc6,0xff,0xff,0xaf,0xeb,0xfa,0xee,0xbf,0xab,0x7a,0xbe,0xaf,0xad,0xeb,
- 0xfa,0xf9,0xdd,0xff,0xff,0xff,0xff,0xff,0xb3,0xef,0xff,0xff,0xff,0xff,0xfe,0xbf,
- 0xff,0xff,0xf1,0xff,0xff,0xff,0xff,0xff,0xaf,0xfe,0x7f,0xef,0xff,0xff,0xfb,0xf7,
- 0xff,0xfe,0x47,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xdf,0x67,0xff,0xff,0xbf,0xff,0xff,0xf7,0xbd,0xff,0xff,0xff,0xff,0xfb,0xdf,
- 0xff,0xff,0x5f,0xfd,0xff,0xff,0xff,0xff,0xdf,0xdf,0xdf,0xdf,0xf7,0xff,0xdf,0xff,
- 0xff,0xdc,0x1f,0xff,0xff,0xf7,0xff,0xff,0x7f,0xed,0xbd,0xff,0xbf,0xff,0xff,0xff,
- 0xff,0xf4,0x7f,0xf7,0xff,0xff,0xff,0xff,0xff,0xbf,0x7f,0xff,0xff,0xbe,0xff,0xff,
- 0xff,0xe6,0xfb,0xff,0xff,0xff,0xff,0xff,0xf7,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xdd,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0xf7,0xbf,0xef,0xff,0xff,0xff,
- 0xff,0xbb,0xef,0xff,0xff,0xff,0xff,0xff,0x3f,0xfb,0xff,0xfe,0xff,0xff,0xff,0xff,
- 0xff,0x37,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
- 0xfe,0x0f,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x77,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xfa,0x5f,0xfe,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
- 0xff,0x8f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xcb,0x6b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
- 0x6c,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
- 0xc9,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
- 0xc3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
- 0xd6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,
- 0x07,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,
- 0x1f,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
- 0x3e,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
- 0x7d,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf2,
- 0x7f,0xee,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xad,
- 0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xf3,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc7,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x8f,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xec,0xcf,
- 0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x3f,
- 0xff,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xfa,0x7f,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe8,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xe1,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xa3,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb7,0xff,
- 0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xcf,0xff,
- 0xfa,0xfe,0xbf,0xa7,0xeb,0xfa,0xff,0xa7,0xeb,0xfa,0xdc,0xbf,0xaf,0xf5,0x9f,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0x9f,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xe9,0x7f,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xef,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x7f,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xfe,0xfe,0xfe,0xff,0xff,0xfd,0xfd,0xff,0xdd,0xff,0xff,
- 0xff,0xdf,0xff,0xff,0x7f,0xfc,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0x91,0xff,0xf1,
- 0xff,0xff,0xff,0x7f,0xff,0x7b,0x3f,0x7b,0xff,0xff,0xff,0xfd,0xff,0x17,0xff,0xdf,
- 0x7e,0xff,0xbf,0xff,0xbf,0xd1,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xef,0xff,0xef,
- 0xff,0xff,0xff,0xff,0xff,0xeb,0xfb,0xff,0xff,0xff,0xff,0xff,0xfc,0x5f,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xde,0xf7,0xff,0xff,0xff,0xbf,0xff,0xfe,0x3f,0xff,0xff,
- 0xff,0xff,0xdf,0xff,0xff,0xbf,0xff,0xff,0xff,0xfd,0xff,0xff,0xf8,0x7f,0xfd,0x77,
- 0xfd,0xff,0xdf,0xff,0xeb,0xb7,0xff,0xff,0xff,0xff,0xfd,0xff,0xee,0xff,0xfe,0xff,
- 0xef,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xa5,0xff,0xfb,0xff,
- 0xf7,0xff,0xff,0x7f,0xfe,0x7f,0xff,0xff,0xff,0xff,0xfd,0xff,0xe3,0xbf,0xf9,0xfe,
- 0x7f,0x9f,0xe7,0xf9,0xfc,0x1f,0xe7,0xf9,0xf8,0x7f,0x9f,0xfe,0xd7,0xff,0xfb,0xfe,
- 0xde,0xbd,0xed,0xeb,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,0xaf,0xfe,0xcf,0xff,0xe7,0xf9,
- 0xff,0x7f,0x9f,0xe3,0xff,0xff,0xbf,0xef,0xfb,0xce,0xff,0xfe,0x9f,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xfb,0xbf,0xff,0xbf,0xeb,
- 0xfb,0xde,0xff,0xb7,0xdb,0xfe,0xff,0xbf,0xef,0xfb,0x7f,0xfc,0x7f,0xfc,0xff,0x3f,
- 0xcf,0xf3,0xfc,0xdf,0xcf,0xf3,0xfc,0xff,0x3f,0x4f,0xff,0xfc,0xef,0xfa,0xfe,0xdf,
- 0xb7,0xeb,0xfb,0x7f,0xbf,0xef,0xfb,0xfe,0xfe,0xbf,0xff,0xdd,0xff,0xf9,0xfe,0xff,
- 0xbf,0xe7,0xfb,0xff,0xb7,0xe5,0xf9,0x7e,0x5f,0x97,0xff,0xfb,0xff,0xf7,0xfd,0x7f,
- 0x7f,0xdf,0xf5,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xff,0xe7,0xff,0xff,0xfd,0xff,
- 0x7f,0xff,0xf7,0xff,0x7f,0xff,0xff,0xff,0xf7,0xff,0xfe,0xef,0xff,0xdf,0x37,0xfd,
- 0xff,0x7f,0xdf,0x6d,0xff,0x7f,0xdf,0xf7,0xed,0xff,0xff,0x9f,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xf7,0xfc,0xbd,0xff,0xdf,0xf7,0xfd,
- 0xff,0x7f,0xdf,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xef,0xf7,0x7b,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xfa,0xf7,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xfe,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xcd,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xfd,0xff,0xcf,0xff,0xff,0xff,0xbf,0xfb,0xe3,0xff,0xff,0xfd,0xfb,0x7f,
- 0xff,0xb7,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x87,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xdf,0xff,0xff,0x4f,0xff,0xff,0xef,0xf3,0xff,
- 0xff,0x3f,0xcf,0xff,0xff,0xff,0xff,0xff,0xfe,0xfd,0xdf,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0x7f,0xff,0xfb,0x3e,0x0f,0xbf,
- 0xe0,0xf8,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xe8,0xff,0xfc,0xfe,0x3f,0x0f,0xfb,
- 0xf0,0xfc,0xcf,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xfd,0xff,0xff,0xff,0xff,0xfb,0xff,
- 0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x93,0xff,0xff,0xef,0xbb,0xee,0xbf,
- 0xbe,0xef,0xee,0xbb,0xee,0xfb,0xfe,0xef,0xff,0xe7,0xff,0x76,0xbf,0x3f,0xfb,0xbb,
- 0xfe,0xff,0x7b,0xff,0xbf,0xeb,0xfb,0xde,0x20,0x2f,0xff,0xff,
irq_vecs[vec].count = 0;
}
-#ifdef CONFIG_PPC405GP
- /*--------------------------------------------------------------------------+
- | Interrupt controller setup for the Walnut board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- | IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
- | IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
- | IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- | Note for Walnut board:
- | An interrupt taken for the FPGA (IRQ 25) indicates that either
- | the Mouse, Keyboard, IRDA, or External Expansion caused the
- | interrupt. The FPGA must be read to determine which device
- | caused the interrupt. The default setting of the FPGA clears
- |
- +--------------------------------------------------------------------------*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-
+#ifdef CONFIG_PPC405
/*
* Init PIT
*/
- set_pit(200000);
-#endif
+ set_pit(bd->bi_intfreq * 1000);
+#endif /* CONFIG_PPC405 */
#ifdef CONFIG_ADCIOP
/*
#include <ppcboot.h>
#include <commproc.h>
+#include <asm/processor.h>
/*****************************************************************************/
/*****************************************************************************/
-#ifdef CONFIG_PPC405GP
+#ifdef CONFIG_PPC405
#define UART_BASE_PTR 0xF800FFFC; /* pointer to uart base */
{
volatile char val;
unsigned short br_reg;
+ unsigned long cntrl0Reg;
/*
* Check for sanity
*/
if ((baudrate < CFG_BAUDRATE_MIN) || (baudrate > CFG_BAUDRATE_MAX))
baudrate = CFG_BAUDRATE_DEFAULT;
- br_reg = ((((CONFIG_CPUCLOCK * 1000000)/16)/18) / baudrate);
+
+#ifdef CFG_EXT_SERIAL_CLOCK
+ /*
+ * Use external clock to generate serial clock
+ */
+ cntrl0Reg = mfdcr(cntrl0) & 0xffffe000;
+ cntrl0Reg |= 0x000010c0;
+ mtdcr(cntrl0, cntrl0Reg);
+ br_reg = ((CFG_EXT_SERIAL_CLOCK/16) / baudrate);
+#else
+ /*
+ * Use internal cpu clock to generate serial clock
+ */
+ cntrl0Reg = mfdcr(cntrl0) & 0xffffe000;
+ cntrl0Reg |= 0x00001022;
+ mtdcr(cntrl0, cntrl0Reg); /* serial clock = cpu clock / 18 */
+ br_reg = (((cpu_clock/16)/18) / baudrate);
+#endif
/*
* Init onboard 16550 UART
*/
if ((baudrate < CFG_BAUDRATE_MIN) || (baudrate > CFG_BAUDRATE_MAX))
baudrate = CFG_BAUDRATE_DEFAULT;
- br_reg = ((((CONFIG_CPUCLOCK * 1000000)/16)/18) / baudrate);
+#ifdef CFG_EXT_SERIAL_CLOCK
+ br_reg = ((CFG_EXT_SERIAL_CLOCK/16) / baudrate);
+#else
+ br_reg = (((cpu_clock/16)/18) / baudrate);
+#endif
out8(UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
out8(UART0_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
return 0;
}
-#endif /* CONFIG_PPC405GP */
+#endif /* CONFIG_PPC405 */
#define ONE_BILLION 1000000000
-#ifdef CONFIG_CPCI405
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */
-
-#define IBM405GP_GPIO0_OR 0xef600700 /* GPIO Output */
-#define IBM405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
-#define IBM405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
-#define IBM405GP_GPIO0_IR 0xef60071c /* GPIO Input */
-
-/* fpga configuration data - generated by bit2inc */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-
-/******************************************************************************
- *
- * fpga_boot - Load fpga-image into fpga
- *
- */
-static void fpga_boot(void)
-{
- int i,j,index,len;
- unsigned char b;
- int size = sizeof(fpgadata);
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++)
- {
- len = fpgadata[index];
-#ifdef FPGA_DEBUG
- printf("FPGA: %s\n", &(fpgadata[index+1]));
-#endif
- index += len+3;
- }
-
- /* search for preamble 0xFF2X */
- for (index = 0; index < size-1 ; index++)
- {
- if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x20))
- break;
- }
-#ifdef FPGA_DEBUG
- printf("FPGA: configdata starts at position 0x%x\n",index);
- printf("FPGA: length of fpga-data %d\n", size-index);
-#endif
-
- /*
- * Setup port pins for fpga programming
- */
- out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(IBM405GP_GPIO0_TCR, 0x07000000); /* setup for output */
- out32(IBM405GP_GPIO0_OR, 0x07000000); /* set output pins to high (default) */
-
-#ifdef FPGA_DEBUG
- printf("%s\n",((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0) ? "NOT DONE" : "DONE" );
-#endif
-
- /*
- * Init fpga by asserting and deasserting PROGRAM*
- */
- out32(IBM405GP_GPIO0_OR, 0x03000000);
- udelay(FPGA_PRG_SLEEP*1000);
-#ifdef FPGA_DEBUG
- printf("%s\n",((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0) ? "NOT DONE" : "DONE" );
-#endif
- out32(IBM405GP_GPIO0_OR, 0x07000000);
- udelay(FPGA_PRG_SLEEP*1000);
-#ifdef FPGA_DEBUG
- printf("%s\n",((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0) ? "NOT DONE" : "DONE" );
-#endif
-
- /* write configuration-data into fpga... */
- for (i=index; i<size; i++)
- {
- b = fpgadata[i];
- for (j=0; j<8; j++)
- {
- if ((b & 0x80) == 0x80)
- {
- /*
- * Write 1 to fpga
- */
- out32(IBM405GP_GPIO0_OR, 0x05000000); /* set clock to 0 */
- out32(IBM405GP_GPIO0_OR, 0x05000000); /* set data to 1 */
- out32(IBM405GP_GPIO0_OR, 0x06000000); /* set clock to 1 */
- out32(IBM405GP_GPIO0_OR, 0x07000000); /* set data to 1 */
- }
- else
- {
- /*
- * Write 0 to fpga
- */
- out32(IBM405GP_GPIO0_OR, 0x05000000); /* set clock to 0 */
- out32(IBM405GP_GPIO0_OR, 0x04000000); /* set data to 0 */
- out32(IBM405GP_GPIO0_OR, 0x06000000); /* set clock to 1 */
- out32(IBM405GP_GPIO0_OR, 0x07000000); /* set data to 1 */
- }
-
- /*
- * Shift to next bit
- */
- b <<= 1;
- }
- }
-
- udelay(FPGA_PRG_SLEEP*1000);
-#ifdef FPGA_DEBUG
- printf("%s\n",((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0) ? "NOT DONE" : "DONE" );
-#endif
-
- /*
- * Check if fpga's DONE signal - correctly booted ?
- */
- if ((in32(IBM405GP_GPIO0_IR) & 0x00800000) == 0)
- {
-#ifdef FPGA_DEBUG
- printf("FPGA: Booting failed!\n");
-#endif
- }
- else
- {
-#ifdef FPGA_DEBUG
- printf("FPGA: Booting successful!\n");
-#endif
- }
-}
-#endif
-
-
-#ifdef CONFIG_PPC405GP
+#ifdef CONFIG_PPC405
void get_sys_info (PPC405_SYS_INFO *sysInfo)
{
unsigned long pllmr;
- unsigned long sysClkPeriodNs = ONE_BILLION / CONFIG_SYS_CLK_FREQ;
+ unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
/*
* Read PLL Mode register
}
else
{
- sysInfo->freqVCOMhz = (1000 * sysInfo->pllFwdDiv * sysInfo->pllFbkDiv *
- sysInfo->pllPlbDiv) / sysClkPeriodNs;
+ sysInfo->freqVCOMhz = (1000000 * sysInfo->pllFwdDiv * sysInfo->pllFbkDiv *
+ sysInfo->pllPlbDiv) / sysClkPeriodPs;
if (sysInfo->freqVCOMhz >= VCO_MIN && sysInfo->freqVCOMhz <= VCO_MAX)
{
sysInfo->freqPLB = (ONE_BILLION /
- ((sysClkPeriodNs * 10) / sysInfo->pllFbkDiv)) * 10;
+ ((sysClkPeriodPs * 10) / sysInfo->pllFbkDiv)) * 10000;
sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
}
else
}
}
-#endif /* CONFIG_PPC405GP */
+#endif /* CONFIG_PPC405 */
ulong get_gclk_freq (void)
{
ulong val;
-#ifdef CONFIG_PPC405GP
+#ifdef CONFIG_PPC405
PPC405_SYS_INFO sys_info;
get_sys_info(&sys_info);
val = sys_info.freqProcessor;
-
-#ifdef CONFIG_CPCI405
- /*
- * Boot onboard FPGA
- */
- fpga_boot();
-#endif /* CONFIG_CPCI405 */
-#endif /* CONFIG_PPC405GP */
+#endif /* CONFIG_PPC405 */
#ifdef CONFIG_IOP480
val = 66000000;
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
+
+ .extern ext_bus_cntlr_init
+ .extern sdram_init
+
/*
* Set up GOT: Global Offset Table
*
#endif /* CONFIG_IOP480 */
/*****************************************************************************/
-#ifdef CONFIG_PPC405GP
+#ifdef CONFIG_PPC405
//-----------------------------------------------------------------------
// Clear and set up some registers.
mttcr r4 // clear Timer Control Reg
mtxer r4 // clear Fixed-Point Exception Reg
mtevpr r4 // clear Exception Vector Prefix Reg
-#if 1 /* test-only */
- addi r4,r0,0x1000 // set ME bit (Machine Exceptions)
- oris r4,r4,0x0002 // set CE bit (Critical Exceptions)
+ addi r4,r0,0x1000 // set ME bit (Machine Exceptions)
+ oris r4,r4,0x0002 // set CE bit (Critical Exceptions)
mtmsr r4 // change MSR
-#else /* problems in rom2ram (see test-only in rom2ram!!!) */
- addi r4,r0,0x0000 // dont set (!!!) ME bit (Machine Exceptions)
- oris r4,r4,0x0002 // set CE bit (Critical Exceptions)
- mtmsr r4 // change MSR
-#endif
addi r4,r0,(0xFFFF-0x10000) // set r4 to 0xFFFFFFFF (status in the
// dbsr is cleared by setting bits to 1)
mtdbsr r4 // clear/reset the dbsr
addis r4,r0,0x8000
addi r4,r4,0x0001
mticcr r4 // instruction cache
+ isync
addis r4,r0,0x0000
addi r4,r4,0x0000
//-----------------------------------------------------------------------
bl ext_bus_cntlr_init
- //-----------------------------------------------------------------------
- // Initialize the On Chip Memory (4k SRAM)
- //-----------------------------------------------------------------------
- addis r4,r0,OCM_DATA_ADDR@h
- ori r4,r4,OCM_DATA_ADDR@l
- mtdcr ocmdsarc,r4
- addis r4,r0,0xc000
- ori r4,r4,0x0000
- mtdcr ocmdscntl,r4
-
- //-----------------------------------------------------------------------
- // Initialize the Control 0 register for UART control.
- // Set UART1 for CTS/RTS and set the UART0 and UART1 internal
- // clock enable to use the internal serial clock instead of an
- // external clock. Set the FPGA control reg for UART1 to
- // select CTS/RTS.
- //-----------------------------------------------------------------------
- addis r3,r0,0x0000 // set CTS/RTS for UART1 and set int.
- ori r3,r3,0x1022 // clock for UART0 and UART1 (/ 18)
- mtdcr cntrl0,r3 // set CNTRL0
-
//-----------------------------------------------------------------------
// Initialize SDRAM Controller
//-----------------------------------------------------------------------
bl sdram_init
addis r1,r0,CFG_INIT_RAM_ADDR@h
- ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in internal SRAM */
+ ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
GET_GOT /* initialize GOT access */
bl board_init_f /* run first part of init code (from Flash) */
-#endif /* CONFIG_PPC405GP */
+#endif /* CONFIG_PPC405 */
.globl _start_of_vectors
stw r0, 4(r7)
blr
-
-
-#ifdef CONFIG_PPC405GP
-
-//-----------------------------------------------------------------------------
-// Function: ext_bus_cntlr_init
-// Description: Initializes the External Bus Controller for the external
-// peripherals. IMPORTANT: For pass1 this code must run from
-// cache since you can not reliably change a peripheral banks
-// timing register (pbxap) while running code from that bank.
-// For ex., since we are running from ROM on bank 0, we can NOT
-// execute the code that modifies bank 0 timings from ROM, so
-// we run it from cache.
-// Bank 0 - Flash bank 0
-// Bank 1 - Flash bank 1
-// Bank 2 - CAN0, CAN1, CAN2, Codeswitch (0x000,0x100,0x200,0x400)
-// Bank 3 - IDE (CompactFlash)
-// Bank 4 - Quart
-// Bank 5 - not used
-// Bank 6 - not used
-// Bank 7 - not used
-//-----------------------------------------------------------------------------
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- addis r4,r0,0x8000
- ori r4,r4,0x0001
-
- mficcr r9 // get iccr value
- cmp cr0,0,r9,r4 // check if caching already enabled
- beq ..icache_on // if not,
- mticcr r4 // enable caching
-..icache_on:
-#if 0 /* test-only */
- addis r3,0,ext_bus_cntlr_init@h // store the address of the
- ori r3,r3,ext_bus_cntlr_init@l // ext_bus_cntlr_init functn in r3
-#else
- addis r3,0,0xfffd // store the address of the
- ori r3,r3,0x24ec // ext_bus_cntlr_init functn in r3
-#endif
- addi r4,0,14 // set ctr to 10; used to prefetch
- mtctr r4 // 10 cache lines to fit this function
- // in cache (gives us 8x10=80 instrctns)
-..ebcloop:
- icbt r0,r3 // prefetch cache line for addr in r3
- addi r3,r3,32 // move to next cache line
- bdnz ..ebcloop // continue for 10 cache lines
-
- //-------------------------------------------------------------------
- // Delay to ensure all accesses to ROM are complete before changing
- // bank 0 timings. 200usec should be enough.
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp:
- bdnz ..spinlp // spin loop
-
- //-----------------------------------------------------------------------
- // Memory Bank 0 (Flash Bank 0) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x9201
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
-// addis r4,0,0xFFE3 // BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),
- addis r4,0,0xFFC5 // BAS=0xFFC,BS=0x2(4MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 1 (Flash Bank 1) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb1ap
- mtdcr ebccfga,r4
- addis r4,0,0x9201
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
-
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
-// addis r4,0,0xFFC3 // BAS=0xFFC,BS=0x1(2MB),BU=0x3(R/W),
- addis r4,0,0xFF85 // BAS=0xFF8,BS=0x2(4MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb2ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x53c0 // enable Ready, BEM=1
- mtdcr ebccfgd,r4
-
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
- addis r4,0,0xF001 // BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 3 (CompactFlash IDE) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb3ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x53c0 // enable Ready, BEM=1
- mtdcr ebccfgd,r4
-
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
- addis r4,0,0xF011 // BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 4 (NVRAM) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb4ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x5280 // disable Ready, BEM=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb4cr
- mtdcr ebccfga,r4
- addis r4,0,0xF021 // BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 5 (Quart) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb5ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x5280 // disable Ready, BEM=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb5cr
- mtdcr ebccfga,r4
- addis r4,0,0xF031 // BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- cmpi cr0,0,r9,0x0 // check if I cache was off when we
- // started
- bne ..ebc_done // if it was on, leave on
- addis r4,r0,0x0000 // if it was off, disable
- mticcr r4 // restore iccr
- isync
-..ebc_done:
- nop // pass2 DCR errata #8
- blr
-
-//-----------------------------------------------------------------------------
-// Function: sdram_init
-// Description: Configures SDRAM memory banks.
-// Auto Memory Configuration option reads the SDRAM EEPROM
-// via the IIC bus and then configures the SDRAM memory
-// banks appropriately. If Auto Memory Configuration is
-// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
-// plugged, ie. the DIMM that shipped wih the Eval board.
-//-----------------------------------------------------------------------------
- .globl sdram_init
-
-sdram_init:
-
- mflr r31
-
- //-------------------------------------------------------------------
- // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
- //-------------------------------------------------------------------
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,0x0004
- ori r4,r4,0x6001
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
- // To set the appropriate timings, we need to know the SDRAM speed.
- // We can use the PLB speed since the SDRAM speed is the same as
- // the PLB speed. The PLB speed is the FBK divider times the
- // 405GP reference clock, which on the Walnut board is 33Mhz.
- // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is
- // 100Mhz; if FBK is 3, SDRAM is 133Mhz.
- // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and
- // maybe 133Mhz.
- //-------------------------------------------------------------------
- mfdcr r5,strap // determine FBK divider
- // via STRAP reg to calc PLB speed.
- // SDRAM speed is the same as the PLB
- // speed.
- rlwinm r4,r5,4,0x3 // get FBK divide bits
-
-..chk_66:
- cmpi %cr0,0,r4,0x1
- bne ..chk_100
- addis r6,0,0x0085 // SDTR1 value for 66Mhz
- ori r6,r6,0x4005
- addis r7,0,0x03F8 // RTR value for 66Mhz
- b ..sdram_ok
-..chk_100:
- cmpi %cr0,0,r4,0x2
- bne ..chk_133
- addis r6,0,0x0086 // SDTR1 value for 100Mhz
- ori r6,r6,0x400D
- addis r7,0,0x05F0 // RTR value for 100Mhz
- b ..sdram_ok
-..chk_133:
- addis r6,0,0x0107 // SDTR1 value for 133Mhz
- ori r6,r6,0x4015
- addis r7,0,0x07F0 // RTR value for 133Mhz
-
-..sdram_ok:
- //-------------------------------------------------------------------
- // Set SDTR1
- //-------------------------------------------------------------------
- addi r4,0,mem_sdtr1
- mtdcr memcfga,r4
- mtdcr memcfgd,r6
-
- //-------------------------------------------------------------------
- // Set RTR
- //-------------------------------------------------------------------
- addi r4,0,mem_rtr
- mtdcr memcfga,r4
- mtdcr memcfgd,r7
-
- //-------------------------------------------------------------------
- // Delay to ensure 200usec have elapsed since reset. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0000
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 // spin loop
-
- //-------------------------------------------------------------------
- // Set memory controller options reg, MCOPT1.
- // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- // read/prefetch.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 // set DC_EN=1
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Delay to ensure 10msec have elapsed since reset. This is
- // required for the MPC952 to stabalize. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
- // This delay should occur before accessing SDRAM.
- //-------------------------------------------------------------------
- addis r3,0,0x001E
- ori r3,r3,0x8480 // ensure 10msec have passed since reset
- mtctr r3
-..spinlp3:
- bdnz ..spinlp3 // spin loop
-
- mtlr r31 // restore lr
- blr
-
-#endif /* CONFIG_PPC405GP */
-
#define PVR_405GP_RB 0x40110040
#define PVR_405GP_RC 0x40110082
#define PVR_405GP_RD 0x401100C4
+#define PVR_405CR_RA 0x40110041
+#define PVR_405CR_RB 0x401100C5
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_PPC405GP 1 /* This is a PPC405GP CPU */
+#define CONFIG_PPC405 1 /* ...member of PPC405 family */
+#define CONFIG_AR405 1 /* ...on a AR405 board */
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#if 1
+#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
+#else
+#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
+#endif
+
+#if 0
+#define CONFIG_BOOTARGS "root=/dev/nfs " \
+ "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
+ "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
+#else
+#define CONFIG_BOOTARGS "root=/dev/hda1 " \
+ "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
+
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_PCI_PNP 1 /* include pci plug-and-play */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
+#define CFG_BAUDRATE_MIN 300 /* lowest possible baudrate */
+#define CFG_BAUDRATE_MAX 115200 /* highest possible baudrate */
+#define CFG_BAUDRATE_DEFAULT CONFIG_BAUDRATE /* default baudrate */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFFD0000
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+
+#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
+
+
+/* On Chip Memory location */
+#define OCM_DATA_ADDR 0xF8000000
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in RAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x8000 /* inside of SDRAM */
+#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_PPC405CR 1 /* This is a PPC405CR CPU */
+#define CONFIG_PPC405 1 /* ...member of PPC405 family */
+#define CONFIG_CANBT 1 /* ...on a CANBT board */
+
+#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
+
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#if 1
+#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
+#else
+#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
+#endif
+
+#if 0
+#define CONFIG_BOOTARGS "root=/dev/nfs " \
+ "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
+ "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
+#else
+#define CONFIG_BOOTARGS "root=/dev/hda1 " \
+ "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
+
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#undef CONFIG_PCI_PNP /* no pci plug-and-play */
+
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IRQ) & ~CFG_CMD_NET)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
+#define CFG_BAUDRATE_MIN 300 /* lowest possible baudrate */
+#define CFG_BAUDRATE_MAX 115200 /* highest possible baudrate */
+#define CFG_BAUDRATE_DEFAULT CONFIG_BAUDRATE /* default baudrate */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFFD0000
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+
+#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
+
+
+/* On Chip Memory location */
+#define OCM_DATA_ADDR 0xF8000000
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in RAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x8000 /* inside of SDRAM */
+#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
*/
#define CONFIG_PPC405GP 1 /* This is a PPC405 CPU */
+#define CONFIG_PPC405 1 /* ...member of PPC405 family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
-#define CONFIG_CPUCLOCK 200
-#define CONFIG_BUSCLOCK 100
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#if 1
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
#endif
#if 0
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/LinuxPPC " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_BOOTARGS "root=/dev/nfs " \
+ "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
+ "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
#else
#define CONFIG_BOOTARGS "root=/dev/hda1 " \
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CFG_BAUDRATE_MIN 300 /* lowest possible baudrate */
#define CFG_BAUDRATE_MAX 115200 /* highest possible baudrate */
#define CFG_BAUDRATE_DEFAULT CONFIG_BAUDRATE /* default baudrate */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR OCM_DATA_ADDR /* On Chip SRAM (4K) */
-#define CFG_INIT_RAM_END 0x0f00 /* End of used area in DPRAM */
+#define CFG_INIT_RAM_ADDR 0x8000 /* inside of SDRAM */
+#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
#define CONFIG_IP860 1 /* ...on a IP860 board */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 19200
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
-/* +0x0282 => 0x02000000 */
#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \
- /*SCCR_RTDIV|*/ /*SCCR_RTSEL|*/ \
+ SCCR_RTDIV | SCCR_RTSEL | \
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
SCCR_EBDF00 | SCCR_DFSYNC00 | \
SCCR_DFBRG00 | SCCR_DFNL000 | \
#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
+ /* Micron Technologies (INTEL compat.) */
#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
unsigned long cpu_clk;
unsigned long reset_status; /* reset status register at boot */
#endif
- unsigned long env_addr; /* Address of Environment struct */
+ unsigned long env_addr; /* Address of Environment struct */
+ unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long relocated; /* Relocat. offset when running in RAM */
mon_fnc_t bi_mon_fnc; /* Monitor functions */
#ifdef CONFIG_8xx
extern ulong load_addr; /* Default Load Address */
/* common/cmd_nvedit.c */
-ulong env_init (void);
+void env_init (init_data_t *);
void env_relocate (ulong);
char *getenv (uchar *);
int getenv_r (uchar *name, uchar *buf, unsigned len);
int flash_write (uchar *, ulong, ulong);
flash_info_t *addr2info (ulong);
-#ifdef CONFIG_CPCI405
+#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405)
/* $(CPU)/405gp_pci.c */
void pci_init (void);
void pciinfo (int);
void hermes_start_lxt980 (int speed);
#endif
+#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || defined(CONFIG_CANBT)
+/* $(BOARD)/$(BOARD).c */
+int board_pre_init (void);
+#endif
+
/* $(CPU)/serial.c */
void serial_init (ulong, int);
void serial_setbrg (ulong, int);
#if defined(CONFIG_8260)
void get_8260_clks (void);
void prt_8260_clks (void);
-#elif defined(CONFIG_8xx) || defined(CONFIG_IOP480) || defined(CONFIG_PPC405GP)
+#elif defined(CONFIG_8xx) || defined(CONFIG_IOP480) || defined(CONFIG_PPC405)
ulong get_gclk_freq (void);
#endif
ulong get_bus_freq (ulong);
-#if defined(CONFIG_PPC405GP)
+#if defined(CONFIG_PPC405)
void get_sys_info (PPC405_SYS_INFO *);
#endif
projects / users / rw / ppcboot.git / commitdiff