Fix ETH56G FC-FEC incorrect Rx offset value by changing it from -255.96
to -469.26 ns.
Those values are derived from HW spec and reflect internal delays.
Hex value is a fixed point representation in Q23.9 format.
Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
                .rx_offset = {
                        .serdes = 0xffffeb27, /* -10.42424 */
                        .no_fec = 0xffffcccd, /* -25.6 */
-                       .fc = 0xfffe0014, /* -255.96 */
+                       .fc = 0xfffc557b, /* -469.26 */
                        .sfd = 0x4a4, /* 2.32 */
                        .bs_ds = 0x32 /* 0.0969697 */
                }