ASoC: mediatek: mt8188: add required clocks

apll2_d4, apll12_div4, top_a2sys and top_aud_iec are possibly used in
the future. To prevent from breaking binding ABI after any mt8188 dts
upstream, add these clocks to clock list in advance.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com
Link: https://lore.kernel.org/r/20230510035526.18137-8-trevor.wu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
index 02411be93900d21279b744d00e30f6b037faab97..4c24d0b9e90d4bd79a35c02d656b707736598ace 100644 (file)
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
@@ -25,14 +25,18 @@ static const char *aud_clks[MT8188_CLK_NUM] = {
 
        /* divider */
        [MT8188_CLK_TOP_APLL1_D4] = "apll1_d4",
+       [MT8188_CLK_TOP_APLL2_D4] = "apll2_d4",
        [MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0",
        [MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1",
        [MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2",
        [MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3",
+       [MT8188_CLK_TOP_APLL12_DIV4] = "apll12_div4",
        [MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9",
 
        /* mux */
        [MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp",
+       [MT8188_CLK_TOP_A2SYS_SEL] = "top_a2sys",
+       [MT8188_CLK_TOP_AUD_IEC_SEL] = "top_aud_iec",
        [MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus",
        [MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h",
        [MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus",

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
index 04cb476f0bcb29092441dddd646da5cd7b198a7f..904505d10841ffa167a9b5f7107eadd8fa898a37 100644 (file)
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
@@ -23,13 +23,17 @@ enum {
        MT8188_CLK_APMIXED_APLL2,
        /* divider */
        MT8188_CLK_TOP_APLL1_D4,
+       MT8188_CLK_TOP_APLL2_D4,
        MT8188_CLK_TOP_APLL12_DIV0,
        MT8188_CLK_TOP_APLL12_DIV1,
        MT8188_CLK_TOP_APLL12_DIV2,
        MT8188_CLK_TOP_APLL12_DIV3,
+       MT8188_CLK_TOP_APLL12_DIV4,
        MT8188_CLK_TOP_APLL12_DIV9,
        /* mux */
        MT8188_CLK_TOP_A1SYS_HP_SEL,
+       MT8188_CLK_TOP_A2SYS_SEL,
+       MT8188_CLK_TOP_AUD_IEC_SEL,
        MT8188_CLK_TOP_AUD_INTBUS_SEL,
        MT8188_CLK_TOP_AUDIO_H_SEL,
        MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL,