x86/cpufeature: Add X86_FEATURE_IA32_ARCH_CAPS and X86_FEATURE_IBRS_ATT

Enumerate future CPU that implements IBRS all the time in its architecture.

Orabug: 27344012
CVE: CVE-2017-5715

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: John Haxby <john.haxby@oracle.com>
Signed-off-by: Kirtikar Kashyap <kirtikar.kashyap@oracle.com>

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 936a01e162b892fd652627b12850eab126e3e1db..8066d416688efc4803938b83a4eb0ca5a5424814 100644 (file)
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -197,6 +197,8 @@
 #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */
 #define X86_FEATURE_INTEL_PT   ( 7*32+15) /* Intel Processor Trace */
 #define X86_FEATURE_SPEC_CTRL  ( 7*32+19) /* Control Speculation Control */
+#define X86_FEATURE_IA32_ARCH_CAPS     ( 7*32+21) /* Control Speculation Control */
+#define X86_FEATURE_IBRS_ATT   ( 7*32+22) /* IBRS all the time */
 
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */

diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 10b03d58389f432dcdc9b29a3c509e1990399b54..50df8b9920158979f68db5ee763c1bae85a36e7f 100644 (file)
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -46,6 +46,7 @@
 
 #define MSR_PLATFORM_INFO              0x000000ce
 #define MSR_MTRRcap                    0x000000fe
+#define MSR_IA32_ARCH_CAPABILITIES     0x0000010a
 #define MSR_IA32_BBL_CR_CTL            0x00000119
 #define MSR_IA32_BBL_CR_CTL3           0x0000011e
 

diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 4bbbee8e69c425f0f890353f34a68e3dc7ca6439..cb5b927a0470d6e08ac347325b149de92d2c4197 100644 (file)
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -48,6 +48,7 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
                { X86_FEATURE_CPB,              CR_EDX, 9, 0x80000007, 0 },
                { X86_FEATURE_PROC_FEEDBACK,    CR_EDX,11, 0x80000007, 0 },
                { X86_FEATURE_SPEC_CTRL,        CR_EDX,26, 0x00000007, 0 },
+               { X86_FEATURE_IA32_ARCH_CAPS,   CR_EDX,29, 0x00000007, 0 },
                { X86_FEATURE_NPT,              CR_EDX, 0, 0x8000000a, 0 },
                { X86_FEATURE_LBRV,             CR_EDX, 1, 0x8000000a, 0 },
                { X86_FEATURE_SVML,             CR_EDX, 2, 0x8000000a, 0 },
@@ -75,4 +76,11 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
                if (regs[cb->reg] & (1 << cb->bit))
                        set_cpu_cap(c, cb->feature);
        }
+
+       if (cpu_has(c, X86_FEATURE_IA32_ARCH_CAPS)) {
+               u64 cap;
+               rdmsrl(MSR_IA32_ARCH_CAPABILITIES, cap);
+               if (cap & 2) /* IBRS all the time */
+                       set_cpu_cap(c, X86_FEATURE_IBRS_ATT);
+       }
 }