drm/amd/display: Trigger DIO FIFO resync on commit streams for DCN32

[WHY and HOW]
Currently, on DCN32 we have an old workaround to resolve a DIO FIFO
speed issue when writing to the OTG DIVIDER register. However, this
workaround is not safe as we should be applying the DIO FIFO rampup
logic when the OTG re disabled along with the encoders. This new
workaround accounts for this. If the workaround sequence is incorrect,
like it is was, there is a chance we might hang. this new
workaround was first implemented in DCN314.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Saaem Rizvi <syedsaaem.rizvi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index 70fac2ebb757696c3282f22b3fc264c5bf689437..46b6f4f9e1fd1ac7c7f4316da0d44845ee9d84c0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -412,6 +412,8 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc
        hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
                if (otg_disabled[i])
                        pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
        }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index ffbb739d85b6923aacf49024b2925928709a1149..11e28e056cf7c61e780755e53af2a9bbb82a88d3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -42,18 +42,14 @@
 #define DC_LOGGER \
        dccg->ctx->logger
 
-/* This function is a workaround for writing to OTG_PIXEL_RATE_DIV
- * without the probability of causing a DIG FIFO error.
- */
-static void dccg32_wait_for_dentist_change_done(
+static void dccg32_trigger_dio_fifo_resync(
        struct dccg *dccg)
 {
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+       uint32_t dispclk_rdivider_value = 0;
 
-       uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);
-
-       REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);
-       REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
+       REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value);
+       REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);
 }
 
 static void dccg32_get_pixel_rate_div(
@@ -124,29 +120,21 @@ static void dccg32_set_pixel_rate_div(
                REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
                                OTG0_PIXEL_RATE_DIVK1, k1,
                                OTG0_PIXEL_RATE_DIVK2, k2);
-
-               dccg32_wait_for_dentist_change_done(dccg);
                break;
        case 1:
                REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
                                OTG1_PIXEL_RATE_DIVK1, k1,
                                OTG1_PIXEL_RATE_DIVK2, k2);
-
-               dccg32_wait_for_dentist_change_done(dccg);
                break;
        case 2:
                REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
                                OTG2_PIXEL_RATE_DIVK1, k1,
                                OTG2_PIXEL_RATE_DIVK2, k2);
-
-               dccg32_wait_for_dentist_change_done(dccg);
                break;
        case 3:
                REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
                                OTG3_PIXEL_RATE_DIVK1, k1,
                                OTG3_PIXEL_RATE_DIVK2, k2);
-
-               dccg32_wait_for_dentist_change_done(dccg);
                break;
        default:
                BREAK_TO_DEBUGGER();
@@ -352,6 +340,7 @@ static const struct dccg_funcs dccg32_funcs = {
        .otg_add_pixel = dccg32_otg_add_pixel,
        .otg_drop_pixel = dccg32_otg_drop_pixel,
        .set_pixel_rate_div = dccg32_set_pixel_rate_div,
+       .trigger_dio_fifo_resync = dccg32_trigger_dio_fifo_resync,
 };
 
 struct dccg *dccg32_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
index 8071ab98d7084b4b9a19629785e0dbf4459107bc..cf5508718122248a3c1488f54b418bdbd47e9eba 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
@@ -112,8 +112,9 @@
        DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
        DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
        DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
-       DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
-
+       DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\
+       DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, mask_sh),\
+       DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh)
 
 struct dccg *dccg32_create(
        struct dc_context *ctx,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 2de910e0ce75f60ce39f10ea4d151ec1693a868a..7f5cd8c8d49b7e35516fdc5a0e111b26e48820d4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1175,6 +1175,35 @@ void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
                                pix_per_cycle);
 }
 
+void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
+{
+       uint8_t i;
+       struct pipe_ctx *pipe = NULL;
+       bool otg_disabled[MAX_PIPES] = {false};
+
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+               if (pipe->top_pipe || pipe->prev_odm_pipe)
+                       continue;
+
+               if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
+                       pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
+                       reset_sync_context_for_pipe(dc, context, i);
+                       otg_disabled[i] = true;
+               }
+       }
+
+       hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
+
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+               if (otg_disabled[i])
+                       pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+       }
+}
+
 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
                struct dc_link_settings *link_settings)
 {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
index 6694c1d14aa31d97db0734e5af9649eb8ea3fbb6..6dbe929cf599adbf0d383d29ddd71c416918cd8d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
@@ -75,6 +75,8 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign
 
 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
 
+void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
+
 void dcn32_subvp_pipe_control_lock(struct dc *dc,
                struct dc_state *context,
                bool lock,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
index 6f9a165c1eab90e5c0173b3776cd9b175fdac8a2..8356b31e1d9afc9fdc29dfd349719c12d8b9e737 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -153,6 +153,7 @@ static const struct hwseq_private_funcs dcn32_private_funcs = {
        .update_mall_sel = dcn32_update_mall_sel,
        .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
        .set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
+       .resync_fifo_dccg_dio = dcn32_resync_fifo_dccg_dio,
        .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
 };