#include <asm/swiotlb.h>
 
 /* Some dma direct funcs must be visible for use in other dma_ops */
-extern void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
+extern void *__dma_nommu_alloc_coherent(struct device *dev, size_t size,
                                         dma_addr_t *dma_handle, gfp_t flag,
                                         unsigned long attrs);
-extern void __dma_direct_free_coherent(struct device *dev, size_t size,
+extern void __dma_nommu_free_coherent(struct device *dev, size_t size,
                                       void *vaddr, dma_addr_t dma_handle,
                                       unsigned long attrs);
-extern int dma_direct_mmap_coherent(struct device *dev,
+extern int dma_nommu_mmap_coherent(struct device *dev,
                                    struct vm_area_struct *vma,
                                    void *cpu_addr, dma_addr_t handle,
                                    size_t size, unsigned long attrs);
 #ifdef CONFIG_PPC64
 extern struct dma_map_ops dma_iommu_ops;
 #endif
-extern const struct dma_map_ops dma_direct_ops;
+extern const struct dma_map_ops dma_nommu_ops;
 
 static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
 {
 
 struct dma_map_ops dma_iommu_ops = {
        .alloc                  = dma_iommu_alloc_coherent,
        .free                   = dma_iommu_free_coherent,
-       .mmap                   = dma_direct_mmap_coherent,
+       .mmap                   = dma_nommu_mmap_coherent,
        .map_sg                 = dma_iommu_map_sg,
        .unmap_sg               = dma_iommu_unmap_sg,
        .dma_supported          = dma_iommu_dma_supported,
 
  * for everything else.
  */
 const struct dma_map_ops swiotlb_dma_ops = {
-       .alloc = __dma_direct_alloc_coherent,
-       .free = __dma_direct_free_coherent,
-       .mmap = dma_direct_mmap_coherent,
+       .alloc = __dma_nommu_alloc_coherent,
+       .free = __dma_nommu_free_coherent,
+       .mmap = dma_nommu_mmap_coherent,
        .map_sg = swiotlb_map_sg_attrs,
        .unmap_sg = swiotlb_unmap_sg_attrs,
        .dma_supported = swiotlb_dma_supported,
 
        return pfn;
 }
 
-static int dma_direct_dma_supported(struct device *dev, u64 mask)
+static int dma_nommu_dma_supported(struct device *dev, u64 mask)
 {
 #ifdef CONFIG_PPC64
        u64 limit = get_dma_offset(dev) + (memblock_end_of_DRAM() - 1);
 #endif
 }
 
-void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
+void *__dma_nommu_alloc_coherent(struct device *dev, size_t size,
                                  dma_addr_t *dma_handle, gfp_t flag,
                                  unsigned long attrs)
 {
 #endif
 }
 
-void __dma_direct_free_coherent(struct device *dev, size_t size,
+void __dma_nommu_free_coherent(struct device *dev, size_t size,
                                void *vaddr, dma_addr_t dma_handle,
                                unsigned long attrs)
 {
 #endif
 }
 
-static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
+static void *dma_nommu_alloc_coherent(struct device *dev, size_t size,
                                       dma_addr_t *dma_handle, gfp_t flag,
                                       unsigned long attrs)
 {
        /* The coherent mask may be smaller than the real mask, check if
         * we can really use the direct ops
         */
-       if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
-               return __dma_direct_alloc_coherent(dev, size, dma_handle,
+       if (dma_nommu_dma_supported(dev, dev->coherent_dma_mask))
+               return __dma_nommu_alloc_coherent(dev, size, dma_handle,
                                                   flag, attrs);
 
        /* Ok we can't ... do we have an iommu ? If not, fail */
                                    dev_to_node(dev));
 }
 
-static void dma_direct_free_coherent(struct device *dev, size_t size,
+static void dma_nommu_free_coherent(struct device *dev, size_t size,
                                     void *vaddr, dma_addr_t dma_handle,
                                     unsigned long attrs)
 {
        struct iommu_table *iommu;
 
-       /* See comments in dma_direct_alloc_coherent() */
-       if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
-               return __dma_direct_free_coherent(dev, size, vaddr, dma_handle,
+       /* See comments in dma_nommu_alloc_coherent() */
+       if (dma_nommu_dma_supported(dev, dev->coherent_dma_mask))
+               return __dma_nommu_free_coherent(dev, size, vaddr, dma_handle,
                                                  attrs);
        /* Maybe we used an iommu ... */
        iommu = get_iommu_table_base(dev);
        iommu_free_coherent(iommu, size, vaddr, dma_handle);
 }
 
-int dma_direct_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
+int dma_nommu_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
                             void *cpu_addr, dma_addr_t handle, size_t size,
                             unsigned long attrs)
 {
                               vma->vm_page_prot);
 }
 
-static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
+static int dma_nommu_map_sg(struct device *dev, struct scatterlist *sgl,
                             int nents, enum dma_data_direction direction,
                             unsigned long attrs)
 {
        return nents;
 }
 
-static void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sg,
+static void dma_nommu_unmap_sg(struct device *dev, struct scatterlist *sg,
                                int nents, enum dma_data_direction direction,
                                unsigned long attrs)
 {
 }
 
-static u64 dma_direct_get_required_mask(struct device *dev)
+static u64 dma_nommu_get_required_mask(struct device *dev)
 {
        u64 end, mask;
 
        return mask;
 }
 
-static inline dma_addr_t dma_direct_map_page(struct device *dev,
+static inline dma_addr_t dma_nommu_map_page(struct device *dev,
                                             struct page *page,
                                             unsigned long offset,
                                             size_t size,
        return page_to_phys(page) + offset + get_dma_offset(dev);
 }
 
-static inline void dma_direct_unmap_page(struct device *dev,
+static inline void dma_nommu_unmap_page(struct device *dev,
                                         dma_addr_t dma_address,
                                         size_t size,
                                         enum dma_data_direction direction,
 }
 
 #ifdef CONFIG_NOT_COHERENT_CACHE
-static inline void dma_direct_sync_sg(struct device *dev,
+static inline void dma_nommu_sync_sg(struct device *dev,
                struct scatterlist *sgl, int nents,
                enum dma_data_direction direction)
 {
                __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
 }
 
-static inline void dma_direct_sync_single(struct device *dev,
+static inline void dma_nommu_sync_single(struct device *dev,
                                          dma_addr_t dma_handle, size_t size,
                                          enum dma_data_direction direction)
 {
 }
 #endif
 
-const struct dma_map_ops dma_direct_ops = {
-       .alloc                          = dma_direct_alloc_coherent,
-       .free                           = dma_direct_free_coherent,
-       .mmap                           = dma_direct_mmap_coherent,
-       .map_sg                         = dma_direct_map_sg,
-       .unmap_sg                       = dma_direct_unmap_sg,
-       .dma_supported                  = dma_direct_dma_supported,
-       .map_page                       = dma_direct_map_page,
-       .unmap_page                     = dma_direct_unmap_page,
-       .get_required_mask              = dma_direct_get_required_mask,
+const struct dma_map_ops dma_nommu_ops = {
+       .alloc                          = dma_nommu_alloc_coherent,
+       .free                           = dma_nommu_free_coherent,
+       .mmap                           = dma_nommu_mmap_coherent,
+       .map_sg                         = dma_nommu_map_sg,
+       .unmap_sg                       = dma_nommu_unmap_sg,
+       .dma_supported                  = dma_nommu_dma_supported,
+       .map_page                       = dma_nommu_map_page,
+       .unmap_page                     = dma_nommu_unmap_page,
+       .get_required_mask              = dma_nommu_get_required_mask,
 #ifdef CONFIG_NOT_COHERENT_CACHE
-       .sync_single_for_cpu            = dma_direct_sync_single,
-       .sync_single_for_device         = dma_direct_sync_single,
-       .sync_sg_for_cpu                = dma_direct_sync_sg,
-       .sync_sg_for_device             = dma_direct_sync_sg,
+       .sync_single_for_cpu            = dma_nommu_sync_single,
+       .sync_single_for_device         = dma_nommu_sync_single,
+       .sync_sg_for_cpu                = dma_nommu_sync_sg,
+       .sync_sg_for_device             = dma_nommu_sync_sg,
 #endif
 };
-EXPORT_SYMBOL(dma_direct_ops);
+EXPORT_SYMBOL(dma_nommu_ops);
 
 int dma_set_coherent_mask(struct device *dev, u64 mask)
 {
                 * is no dma_op->set_coherent_mask() so we have to do
                 * things the hard way:
                 */
-               if (get_dma_ops(dev) != &dma_direct_ops ||
+               if (get_dma_ops(dev) != &dma_nommu_ops ||
                    get_iommu_table_base(dev) == NULL ||
                    !dma_iommu_dma_supported(dev, mask))
                        return -EIO;
 
 EXPORT_SYMBOL(isa_mem_base);
 
 
-static const struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
+static const struct dma_map_ops *pci_dma_ops = &dma_nommu_ops;
 
 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
 {
 
 {
        pdev->archdata.dma_mask = DMA_BIT_MASK(32);
        pdev->dev.dma_mask = &pdev->archdata.dma_mask;
-       set_dma_ops(&pdev->dev, &dma_direct_ops);
+       set_dma_ops(&pdev->dev, &dma_nommu_ops);
 }
 
 static __init void print_system_info(void)
 
        return NULL;
 }
 
-static unsigned long cell_dma_direct_offset;
+static unsigned long cell_dma_nommu_offset;
 
 static unsigned long dma_iommu_fixed_base;
 
                                            device_to_mask(dev), flag,
                                            dev_to_node(dev));
        else
-               return dma_direct_ops.alloc(dev, size, dma_handle, flag,
+               return dma_nommu_ops.alloc(dev, size, dma_handle, flag,
                                            attrs);
 }
 
                iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr,
                                    dma_handle);
        else
-               dma_direct_ops.free(dev, size, vaddr, dma_handle, attrs);
+               dma_nommu_ops.free(dev, size, vaddr, dma_handle, attrs);
 }
 
 static dma_addr_t dma_fixed_map_page(struct device *dev, struct page *page,
                                     unsigned long attrs)
 {
        if (iommu_fixed_is_weak == (attrs & DMA_ATTR_WEAK_ORDERING))
-               return dma_direct_ops.map_page(dev, page, offset, size,
+               return dma_nommu_ops.map_page(dev, page, offset, size,
                                               direction, attrs);
        else
                return iommu_map_page(dev, cell_get_iommu_table(dev), page,
                                 unsigned long attrs)
 {
        if (iommu_fixed_is_weak == (attrs & DMA_ATTR_WEAK_ORDERING))
-               dma_direct_ops.unmap_page(dev, dma_addr, size, direction,
+               dma_nommu_ops.unmap_page(dev, dma_addr, size, direction,
                                          attrs);
        else
                iommu_unmap_page(cell_get_iommu_table(dev), dma_addr, size,
                           unsigned long attrs)
 {
        if (iommu_fixed_is_weak == (attrs & DMA_ATTR_WEAK_ORDERING))
-               return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs);
+               return dma_nommu_ops.map_sg(dev, sg, nents, direction, attrs);
        else
                return ppc_iommu_map_sg(dev, cell_get_iommu_table(dev), sg,
                                        nents, device_to_mask(dev),
                               unsigned long attrs)
 {
        if (iommu_fixed_is_weak == (attrs & DMA_ATTR_WEAK_ORDERING))
-               dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs);
+               dma_nommu_ops.unmap_sg(dev, sg, nents, direction, attrs);
        else
                ppc_iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents,
                                   direction, attrs);
 {
        if (get_pci_dma_ops() == &dma_iommu_ops)
                set_iommu_table_base(dev, cell_get_iommu_table(dev));
-       else if (get_pci_dma_ops() == &dma_direct_ops)
-               set_dma_offset(dev, cell_dma_direct_offset);
+       else if (get_pci_dma_ops() == &dma_nommu_ops)
+               set_dma_offset(dev, cell_dma_nommu_offset);
        else
                BUG();
 }
        unsigned long base = 0, size;
 
        /* When no iommu is present, we use direct DMA ops */
-       set_pci_dma_ops(&dma_direct_ops);
+       set_pci_dma_ops(&dma_nommu_ops);
 
        /* First make sure all IOC translation is turned off */
        cell_disable_iommus();
 
        /* If we have no Axon, we set up the spider DMA magic offset */
        if (of_find_node_by_name(NULL, "axon") == NULL)
-               cell_dma_direct_offset = SPIDER_DMA_OFFSET;
+               cell_dma_nommu_offset = SPIDER_DMA_OFFSET;
 
        /* Now we need to check to see where the memory is mapped
         * in PCI space. We assume that all busses use the same dma
                return -ENODEV;
        }
 
-       cell_dma_direct_offset += base;
+       cell_dma_nommu_offset += base;
 
-       if (cell_dma_direct_offset != 0)
+       if (cell_dma_nommu_offset != 0)
                cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup;
 
        printk("iommu: disabled, direct DMA offset is 0x%lx\n",
-              cell_dma_direct_offset);
+              cell_dma_nommu_offset);
 
        return 0;
 }
 
         */
        if (dev->vendor == 0x1959 && dev->device == 0xa007 &&
            !firmware_has_feature(FW_FEATURE_LPAR)) {
-               dev->dev.dma_ops = &dma_direct_ops;
+               dev->dev.dma_ops = &dma_nommu_ops;
                /*
                 * Set the coherent DMA mask to prevent the iommu
                 * being used unnecessarily
 
                return 0;
 
        /* We use the direct ops for localbus */
-       dev->dma_ops = &dma_direct_ops;
+       dev->dma_ops = &dma_nommu_ops;
 
        return 0;
 }
 
 
        if (bypass) {
                dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
-               set_dma_ops(&pdev->dev, &dma_direct_ops);
+               set_dma_ops(&pdev->dev, &dma_nommu_ops);
        } else {
                /*
                 * If the device can't set the TCE bypass bit but still wants
                                return rc;
                        /* 4GB offset bypasses 32-bit space */
                        set_dma_offset(&pdev->dev, (1ULL << 32));
-                       set_dma_ops(&pdev->dev, &dma_direct_ops);
+                       set_dma_ops(&pdev->dev, &dma_nommu_ops);
                } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
                        /*
                         * Fail the request if a DMA mask between 32 and 64 bits
 
                        if (dma_offset != 0) {
                                dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
                                set_dma_offset(dev, dma_offset);
-                               set_dma_ops(dev, &dma_direct_ops);
+                               set_dma_ops(dev, &dma_nommu_ops);
                                ddw_enabled = true;
                        }
                }
 
 static const struct dma_map_ops vio_dma_mapping_ops = {
        .alloc             = vio_dma_iommu_alloc_coherent,
        .free              = vio_dma_iommu_free_coherent,
-       .mmap              = dma_direct_mmap_coherent,
+       .mmap              = dma_nommu_mmap_coherent,
        .map_sg            = vio_dma_iommu_map_sg,
        .unmap_sg          = vio_dma_iommu_unmap_sg,
        .map_page          = vio_dma_iommu_map_page,
 
         */
        if (dart_device_on_pcie(dev) && dma_mask >= DMA_BIT_MASK(40)) {
                dev_info(dev, "Using 64-bit DMA iommu bypass\n");
-               set_dma_ops(dev, &dma_direct_ops);
+               set_dma_ops(dev, &dma_nommu_ops);
        } else {
                dev_info(dev, "Using 32-bit DMA via iommu\n");
                set_dma_ops(dev, &dma_iommu_ops);
        controller_ops->dma_bus_setup = NULL;
 
        /* Setup pci_dma ops */
-       set_pci_dma_ops(&dma_direct_ops);
+       set_pci_dma_ops(&dma_nommu_ops);
 }
 
 #ifdef CONFIG_PM
 
         * mapping that allows addressing any RAM address from across PCI.
         */
        if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) {
-               set_dma_ops(dev, &dma_direct_ops);
+               set_dma_ops(dev, &dma_nommu_ops);
                set_dma_offset(dev, pci64_dma_offset);
        }
 
 
                return false;
        }
 
-       set_dma_ops(&dev->dev, &dma_direct_ops);
+       set_dma_ops(&dev->dev, &dma_nommu_ops);
        set_dma_offset(&dev->dev, PAGE_OFFSET);
 
        return _cxl_pci_associate_default_context(dev, afu);