clk: sunxi-ng: Add check for minimal rate to NM PLLs

Some NM PLLs doesn't work well when their output clock rate is set below
certain rate.

Add support for that constrain.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index a16de092bf94d408c960e347183bb3603d7f542c..4e2073307f34013e215fd827cc7048f6d4608bc6 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -117,6 +117,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
        if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
                rate *= nm->fixed_post_div;
 
+       if (rate < nm->min_rate) {
+               rate = nm->min_rate;
+               if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+                       rate /= nm->fixed_post_div;
+               return rate;
+       }
+
        if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
                if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
                        rate /= nm->fixed_post_div;

diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
index eba586b4c7d0d5863d29e922b5241bb21c23177a..1d8b459c50b7c8d90e2085eeacc402c61989641c 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu_nm.h
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -37,6 +37,7 @@ struct ccu_nm {
        struct ccu_sdm_internal         sdm;
 
        unsigned int            fixed_post_div;
+       unsigned int            min_rate;
 
        struct ccu_common       common;
 };
@@ -88,6 +89,32 @@ struct ccu_nm {
                },                                                      \
        }
 
+#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent,  \
+                                            _reg, _min_rate,           \
+                                            _nshift, _nwidth,          \
+                                            _mshift, _mwidth,          \
+                                            _frac_en, _frac_sel,       \
+                                            _frac_rate_0, _frac_rate_1,\
+                                            _gate, _lock, _flags)      \
+       struct ccu_nm _struct = {                                       \
+               .enable         = _gate,                                \
+               .lock           = _lock,                                \
+               .n              = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
+               .m              = _SUNXI_CCU_DIV(_mshift, _mwidth),     \
+               .frac           = _SUNXI_CCU_FRAC(_frac_en, _frac_sel,  \
+                                                 _frac_rate_0,         \
+                                                 _frac_rate_1),        \
+               .min_rate       = _min_rate,                            \
+               .common         = {                                     \
+                       .reg            = _reg,                         \
+                       .features       = CCU_FEATURE_FRACTIONAL,       \
+                       .hw.init        = CLK_HW_INIT(_name,            \
+                                                     _parent,          \
+                                                     &ccu_nm_ops,      \
+                                                     _flags),          \
+               },                                                      \
+       }
+
 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg,     \
                                    _nshift, _nwidth,                   \
                                    _mshift, _mwidth,                   \