]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
net/mlx5: kTLS, Improve TLS params layout structures
authorTariq Toukan <tariqt@mellanox.com>
Fri, 26 Jun 2020 05:59:43 +0000 (22:59 -0700)
committerSaeed Mahameed <saeedm@mellanox.com>
Sat, 27 Jun 2020 20:50:46 +0000 (13:50 -0700)
Add explicit WQE segment structures for the TLS static and progress
params.
According to the HW spec, TISN is not part of the progress params context,
take it out of it.
Rename the control segment tisn field as it could hold either a TIS or
a TIR number.

Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.h
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c
drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_rxtx.c
include/linux/mlx5/device.h
include/linux/mlx5/mlx5_ifc.h
include/linux/mlx5/qp.h

index bfd3e1161bc66f0d8c9187ca5a36919ebf4ed814..31cac239563de2946aa11e56a63b7f70960c0cb8 100644 (file)
@@ -182,7 +182,7 @@ mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, void __iomem *uar_map,
 
 static inline bool mlx5e_transport_inline_tx_wqe(struct mlx5_wqe_ctrl_seg *cseg)
 {
-       return cseg && !!cseg->tisn;
+       return cseg && !!cseg->tis_tir_num;
 }
 
 static inline u8
index c6180892cfcbadfb4a9473945569ca91455d0d62..806ed185dd4cfb9a532d713895ea5fcebc9a4a32 100644 (file)
@@ -19,7 +19,7 @@
 
 #define MLX5E_KTLS_PROGRESS_WQE_SZ \
        (offsetof(struct mlx5e_tx_wqe, tls_progress_params_ctx) + \
-        MLX5_ST_SZ_BYTES(tls_progress_params))
+        sizeof(struct mlx5_wqe_tls_progress_params_seg))
 #define MLX5E_KTLS_PROGRESS_WQEBBS \
        (DIV_ROUND_UP(MLX5E_KTLS_PROGRESS_WQE_SZ, MLX5_SEND_WQE_BB))
 
index 3cd78d9503c1228151b47ae67da5a15b1827ce2c..ad7300f198157f634860a7710a1acab8fa862fc6 100644 (file)
@@ -64,7 +64,7 @@ build_static_params(struct mlx5e_umr_wqe *wqe, u16 pc, u32 sqn,
        cseg->qpn_ds           = cpu_to_be32((sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
                                             STATIC_PARAMS_DS_CNT);
        cseg->fm_ce_se         = fence ? MLX5_FENCE_MODE_INITIATOR_SMALL : 0;
-       cseg->tisn             = cpu_to_be32(priv_tx->tisn << 8);
+       cseg->tis_tir_num      = cpu_to_be32(priv_tx->tisn << 8);
 
        ucseg->flags = MLX5_UMR_INLINE;
        ucseg->bsf_octowords = cpu_to_be16(MLX5_ST_SZ_BYTES(tls_static_params) / 16);
@@ -75,10 +75,14 @@ build_static_params(struct mlx5e_umr_wqe *wqe, u16 pc, u32 sqn,
 static void
 fill_progress_params_ctx(void *ctx, struct mlx5e_ktls_offload_context_tx *priv_tx)
 {
-       MLX5_SET(tls_progress_params, ctx, tisn, priv_tx->tisn);
-       MLX5_SET(tls_progress_params, ctx, record_tracker_state,
+       struct mlx5_wqe_tls_progress_params_seg *params;
+
+       params = ctx;
+
+       params->tis_tir_num = cpu_to_be32(priv_tx->tisn);
+       MLX5_SET(tls_progress_params, params->ctx, record_tracker_state,
                 MLX5E_TLS_PROGRESS_PARAMS_RECORD_TRACKER_STATE_START);
-       MLX5_SET(tls_progress_params, ctx, auth_state,
+       MLX5_SET(tls_progress_params, params->ctx, auth_state,
                 MLX5E_TLS_PROGRESS_PARAMS_AUTH_STATE_NO_OFFLOAD);
 }
 
@@ -284,7 +288,7 @@ tx_post_resync_dump(struct mlx5e_txqsq *sq, skb_frag_t *frag, u32 tisn, bool fir
 
        cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8)  | MLX5_OPCODE_DUMP);
        cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | ds_cnt);
-       cseg->tisn             = cpu_to_be32(tisn << 8);
+       cseg->tis_tir_num      = cpu_to_be32(tisn << 8);
        cseg->fm_ce_se         = first ? MLX5_FENCE_MODE_INITIATOR_SMALL : 0;
 
        fsz = skb_frag_size(frag);
index 05454a843b289082dc02066a42de18f0fdc7e681..72d26fbc8d5bfb8081f61b7b4e3d77efb8c1180f 100644 (file)
@@ -305,7 +305,7 @@ err_out:
 void mlx5e_tls_handle_tx_wqe(struct mlx5e_txqsq *sq, struct mlx5_wqe_ctrl_seg *cseg,
                             struct mlx5e_accel_tx_tls_state *state)
 {
-       cseg->tisn = cpu_to_be32(state->tls_tisn << 8);
+       cseg->tis_tir_num = cpu_to_be32(state->tls_tisn << 8);
 }
 
 static int tls_update_resync_sn(struct net_device *netdev,
index 1bc27aca648bbc06c074dd0a7255d7fdc12c0692..57db125e580212acd3a02b3df3b6933c84a252d2 100644 (file)
@@ -458,6 +458,15 @@ enum {
        MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
 };
 
+struct mlx5_wqe_tls_static_params_seg {
+       u8     ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
+};
+
+struct mlx5_wqe_tls_progress_params_seg {
+       __be32 tis_tir_num;
+       u8     ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
+};
+
 enum {
        MLX5_SET_PORT_RESET_QKEY        = 0,
        MLX5_SET_PORT_GUID0             = 16,
index 116bd9bb347f24e69875c2f017264f95264cbac9..a227518c70cf01755c1001bc4534d461598b4e57 100644 (file)
@@ -10638,16 +10638,13 @@ struct mlx5_ifc_tls_static_params_bits {
 };
 
 struct mlx5_ifc_tls_progress_params_bits {
-       u8         reserved_at_0[0x8];
-       u8         tisn[0x18];
-
        u8         next_record_tcp_sn[0x20];
 
        u8         hw_resync_tcp_sn[0x20];
 
        u8         record_tracker_state[0x2];
        u8         auth_state[0x2];
-       u8         reserved_at_64[0x4];
+       u8         reserved_at_44[0x4];
        u8         hw_offset_record_number[0x18];
 };
 
index b8992b861ae6a6a49d5826a5466936cebda72deb..36492a1342cfcdd4513013378e7182dd585a2ac0 100644 (file)
@@ -209,7 +209,7 @@ struct mlx5_wqe_ctrl_seg {
                __be32          general_id;
                __be32          imm;
                __be32          umr_mkey;
-               __be32          tisn;
+               __be32          tis_tir_num;
        };
 };