drm/i915/psr: Unify VSC setup functions.

VSC package is decided per eDP spec for psr1 or psr2,
and not per platform, so let's unify it and kill "skl"
func.

v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
    crtc_state to PSR enable/disable")

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-6-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b3c1e601a8b2f0a3ed38074882fcf64174a99528..eca6170becdce32df67ea9e24e44794a8d3dd03e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -117,46 +117,41 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp,
        I915_WRITE(VLV_VSCSDP(crtc->pipe), val);
 }
 
-static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp,
-                                const struct intel_crtc_state *crtc_state)
+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
+                             const struct intel_crtc_state *crtc_state)
 {
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
        struct edp_vsc_psr psr_vsc;
 
-       /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
-       memset(&psr_vsc, 0, sizeof(psr_vsc));
-       psr_vsc.sdp_header.HB0 = 0;
-       psr_vsc.sdp_header.HB1 = 0x7;
-       if (dev_priv->psr.colorimetry_support &&
-               dev_priv->psr.y_cord_support) {
-               psr_vsc.sdp_header.HB2 = 0x5;
-               psr_vsc.sdp_header.HB3 = 0x13;
-       } else if (dev_priv->psr.y_cord_support) {
-               psr_vsc.sdp_header.HB2 = 0x4;
-               psr_vsc.sdp_header.HB3 = 0xe;
+       if (dev_priv->psr.psr2_support) {
+               /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
+               memset(&psr_vsc, 0, sizeof(psr_vsc));
+               psr_vsc.sdp_header.HB0 = 0;
+               psr_vsc.sdp_header.HB1 = 0x7;
+               if (dev_priv->psr.colorimetry_support &&
+                   dev_priv->psr.y_cord_support) {
+                       psr_vsc.sdp_header.HB2 = 0x5;
+                       psr_vsc.sdp_header.HB3 = 0x13;
+               } else if (dev_priv->psr.y_cord_support) {
+                       psr_vsc.sdp_header.HB2 = 0x4;
+                       psr_vsc.sdp_header.HB3 = 0xe;
+               } else {
+                       psr_vsc.sdp_header.HB2 = 0x3;
+                       psr_vsc.sdp_header.HB3 = 0xc;
+               }
        } else {
-               psr_vsc.sdp_header.HB2 = 0x3;
-               psr_vsc.sdp_header.HB3 = 0xc;
+               /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
+               memset(&psr_vsc, 0, sizeof(psr_vsc));
+               psr_vsc.sdp_header.HB0 = 0;
+               psr_vsc.sdp_header.HB1 = 0x7;
+               psr_vsc.sdp_header.HB2 = 0x2;
+               psr_vsc.sdp_header.HB3 = 0x8;
        }
 
        intel_psr_write_vsc(intel_dp, &psr_vsc);
 }
 
-static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
-                             const struct intel_crtc_state *crtc_state)
-{
-       struct edp_vsc_psr psr_vsc;
-
-       /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
-       memset(&psr_vsc, 0, sizeof(psr_vsc));
-       psr_vsc.sdp_header.HB0 = 0;
-       psr_vsc.sdp_header.HB1 = 0x7;
-       psr_vsc.sdp_header.HB2 = 0x2;
-       psr_vsc.sdp_header.HB3 = 0x8;
-       intel_psr_write_vsc(intel_dp, &psr_vsc);
-}
-
 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 {
        drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
@@ -512,9 +507,10 @@ void intel_psr_enable(struct intel_dp *intel_dp,
        dev_priv->psr.busy_frontbuffer_bits = 0;
 
        if (HAS_DDI(dev_priv)) {
-               if (dev_priv->psr.psr2_support) {
-                       skl_psr_setup_su_vsc(intel_dp, crtc_state);
 
+               hsw_psr_setup_vsc(intel_dp, crtc_state);
+
+               if (dev_priv->psr.psr2_support) {
                        chicken = PSR2_VSC_ENABLE_PROG_HEADER;
                        if (dev_priv->psr.y_cord_support)
                                chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
@@ -527,9 +523,6 @@ void intel_psr_enable(struct intel_dp *intel_dp,
                                   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
                                   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
                } else {
-                       /* set up vsc header for psr1 */
-                       hsw_psr_setup_vsc(intel_dp, crtc_state);
-
                        /*
                         * Per Spec: Avoid continuous PSR exit by masking MEMUP
                         * and HPD. also mask LPSP to avoid dependency on other