arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodes

Add SDHI0-SDHI2 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828124134.188864-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index b1017efdc242591585a835eb831efc5fa6e1b405..9f6939a4e40ff0b1d1a3d6d4cd7eeac9d9541831 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -420,6 +420,45 @@
                        interrupt-controller;
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
                };
+
+               sdhi0: mmc@15c00000  {
+                       compatible = "renesas,sdhi-r9a09g057";
+                       reg = <0x0 0x15c00000 0 0x10000>;
+                       interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
+                                <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg 0xa7>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               sdhi1: mmc@15c10000 {
+                       compatible = "renesas,sdhi-r9a09g057";
+                       reg = <0x0 0x15c10000 0 0x10000>;
+                       interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
+                                <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg 0xa8>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               sdhi2: mmc@15c20000 {
+                       compatible = "renesas,sdhi-r9a09g057";
+                       reg = <0x0 0x15c20000 0 0x10000>;
+                       interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
+                                <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg 0xa9>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
        };
 
        timer {