mt76: mt7615: add missing settings for simultaneous dual-band support

MT7615 supports dual-wiphy which means that it can run on 2.4G and 5GHz
channels simultaneously, and driver should configure each band.

Add missing register settings, and refine band related definitions to
avoid duplicate codes.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>

diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/init.c b/drivers/net/wireless/mediatek/mt76/mt7615/init.c
index c16df56b0717cd696a2b5664a032449050e75e90..a14fd9587b702a747f32f606eafda099e097174f 100644 (file)
--- a/drivers/net/wireless/mediatek/mt76/mt7615/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7615/init.c
@@ -28,17 +28,17 @@ static void mt7615_mac_init(struct mt7615_dev *dev)
                 MT_CFG_CCR_MAC_D0_1X_GC_EN | MT_CFG_CCR_MAC_D0_2X_GC_EN |
                 MT_CFG_CCR_MAC_D1_1X_GC_EN | MT_CFG_CCR_MAC_D1_2X_GC_EN);
 
-       val = mt76_rmw(dev, MT_TMAC_TRCR0,
+       val = mt76_rmw(dev, MT_TMAC_TRCR(0),
                       MT_TMAC_TRCR_CCA_SEL | MT_TMAC_TRCR_SEC_CCA_SEL,
                       FIELD_PREP(MT_TMAC_TRCR_CCA_SEL, 2) |
                       FIELD_PREP(MT_TMAC_TRCR_SEC_CCA_SEL, 0));
-       mt76_wr(dev, MT_TMAC_TRCR1, val);
+       mt76_wr(dev, MT_TMAC_TRCR(1), val);
 
        val = MT_AGG_ACR_PKT_TIME_EN | MT_AGG_ACR_NO_BA_AR_RULE |
              FIELD_PREP(MT_AGG_ACR_CFEND_RATE, MT7615_CFEND_RATE_DEFAULT) |
              FIELD_PREP(MT_AGG_ACR_BAR_RATE, MT7615_BAR_RATE_DEFAULT);
-       mt76_wr(dev, MT_AGG_ACR0, val);
-       mt76_wr(dev, MT_AGG_ACR1, val);
+       mt76_wr(dev, MT_AGG_ACR(0), val);
+       mt76_wr(dev, MT_AGG_ACR(1), val);
 
        mt76_rmw_field(dev, MT_TMAC_CTCR0,
                       MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);
@@ -59,25 +59,27 @@ static void mt7615_mac_init(struct mt7615_dev *dev)
        mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP |
                FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072));
 
-       mt76_wr(dev, MT_AGG_ARUCR,
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1));
-
-       mt76_wr(dev, MT_AGG_ARDCR,
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7615_RATE_RETRY - 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7615_RATE_RETRY - 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7615_RATE_RETRY - 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7615_RATE_RETRY - 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7615_RATE_RETRY - 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7615_RATE_RETRY - 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7615_RATE_RETRY - 1) |
-               FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7615_RATE_RETRY - 1));
+       val = FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1);
+       mt76_wr(dev, MT_AGG_ARUCR(0), val);
+       mt76_wr(dev, MT_AGG_ARUCR(1), val);
+
+       val = FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7615_RATE_RETRY - 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7615_RATE_RETRY - 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7615_RATE_RETRY - 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7615_RATE_RETRY - 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7615_RATE_RETRY - 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7615_RATE_RETRY - 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7615_RATE_RETRY - 1) |
+             FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7615_RATE_RETRY - 1);
+       mt76_wr(dev, MT_AGG_ARDCR(0), val);
+       mt76_wr(dev, MT_AGG_ARDCR(1), val);
 
        mt76_wr(dev, MT_AGG_ARCR,
                (FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) |
@@ -93,8 +95,8 @@ static void mt7615_mac_init(struct mt7615_dev *dev)
               MT_DMA_RCFR0_RX_DROPPED_MCAST;
        set = FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_UCAST, 2) |
              FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_MCAST, 2);
-       mt76_rmw(dev, MT_DMA_BN0RCFR0, mask, set);
-       mt76_rmw(dev, MT_DMA_BN1RCFR0, mask, set);
+       mt76_rmw(dev, MT_DMA_RCFR0(0), mask, set);
+       mt76_rmw(dev, MT_DMA_RCFR0(1), mask, set);
 
        for (i = 0; i < MT7615_WTBL_SIZE; i++)
                mt7615_mac_wtbl_update(dev, i,

diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/mac.c b/drivers/net/wireless/mediatek/mt76/mt7615/mac.c
index 1b52d8b7949639634aa68531c9441424fade5fa8..885a57df76eb658da403e24422f843c72c4e564d 100644 (file)
--- a/drivers/net/wireless/mediatek/mt76/mt7615/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7615/mac.c
@@ -69,7 +69,7 @@ void mt7615_mac_set_timing(struct mt7615_phy *phy)
        s16 coverage_class = phy->coverage_class;
        struct mt7615_dev *dev = phy->dev;
        bool ext_phy = phy != &dev->phy;
-       u32 val, reg_offset, reg = ext_phy ? MT_TMAC_ICR1 : MT_TMAC_ICR0;
+       u32 val, reg_offset;
        u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
                  FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
        u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
@@ -103,7 +103,7 @@ void mt7615_mac_set_timing(struct mt7615_phy *phy)
        mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
        mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
 
-       mt76_wr(dev, reg,
+       mt76_wr(dev, MT_TMAC_ICR(ext_phy),
                FIELD_PREP(MT_IFS_EIFS, 360) |
                FIELD_PREP(MT_IFS_RIFS, 2) |
                FIELD_PREP(MT_IFS_SIFS, sifs) |
@@ -114,15 +114,14 @@ void mt7615_mac_set_timing(struct mt7615_phy *phy)
        else
                val = MT7615_CFEND_RATE_11B;
 
-       if (ext_phy) {
-               mt76_rmw_field(dev, MT_AGG_ACR1, MT_AGG_ACR_CFEND_RATE, val);
+       mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
+       if (ext_phy)
                mt76_clear(dev, MT_ARB_SCR,
                           MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
-       } else {
-               mt76_rmw_field(dev, MT_AGG_ACR0, MT_AGG_ACR_CFEND_RATE, val);
+       else
                mt76_clear(dev, MT_ARB_SCR,
                           MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
-       }
+
 }
 
 int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
@@ -1322,21 +1321,12 @@ mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy)
        struct mt7615_dev *dev = phy->dev;
        bool ext_phy = phy != &dev->phy;
 
-       if (!ext_phy) {
-               mt76_rmw(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
-                        MT_WF_PHY_B0_PD_OFDM_MASK,
-                        MT_WF_PHY_B0_PD_OFDM(0x13c));
-               mt76_rmw(dev, MT_WF_PHY_B0_RXTD_CCK_PD,
-                        MT_WF_PHY_B0_PD_CCK_MASK,
-                        MT_WF_PHY_B0_PD_CCK(0x92));
-       } else {
-               mt76_rmw(dev, MT_WF_PHY_B1_MIN_PRI_PWR,
-                        MT_WF_PHY_B1_PD_OFDM_MASK,
-                        MT_WF_PHY_B1_PD_OFDM(0x13c));
-               mt76_rmw(dev, MT_WF_PHY_B1_RXTD_CCK_PD,
-                        MT_WF_PHY_B1_PD_CCK_MASK,
-                        MT_WF_PHY_B1_PD_CCK(0x92));
-       }
+       mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
+                MT_WF_PHY_PD_OFDM_MASK(ext_phy),
+                MT_WF_PHY_PD_OFDM(ext_phy, 0x13c));
+       mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
+                MT_WF_PHY_PD_CCK_MASK(ext_phy),
+                MT_WF_PHY_PD_CCK(ext_phy, 0x92));
 
        phy->ofdm_sensitivity = -98;
        phy->cck_sensitivity = -110;
@@ -1353,19 +1343,19 @@ void mt7615_mac_set_scs(struct mt7615_dev *dev, bool enable)
                goto out;
 
        if (enable) {
-               mt76_set(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
-                        MT_WF_PHY_B0_PD_BLK);
-               mt76_set(dev, MT_WF_PHY_B1_MIN_PRI_PWR,
-                        MT_WF_PHY_B1_PD_BLK);
+               mt76_set(dev, MT_WF_PHY_MIN_PRI_PWR(0),
+                        MT_WF_PHY_PD_BLK(0));
+               mt76_set(dev, MT_WF_PHY_MIN_PRI_PWR(1),
+                        MT_WF_PHY_PD_BLK(1));
                if (is_mt7622(&dev->mt76)) {
                        mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7 << 8);
                        mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7);
                }
        } else {
-               mt76_clear(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
-                          MT_WF_PHY_B0_PD_BLK);
-               mt76_clear(dev, MT_WF_PHY_B1_MIN_PRI_PWR,
-                          MT_WF_PHY_B1_PD_BLK);
+               mt76_clear(dev, MT_WF_PHY_MIN_PRI_PWR(0),
+                          MT_WF_PHY_PD_BLK(0));
+               mt76_clear(dev, MT_WF_PHY_MIN_PRI_PWR(1),
+                          MT_WF_PHY_PD_BLK(1));
        }
 
        mt7615_mac_set_default_sensitivity(&dev->phy);
@@ -1453,24 +1443,15 @@ mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy,
 
                if (ofdm) {
                        val = *sensitivity * 2 + 512;
-                       if (!ext_phy)
-                               mt76_rmw(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
-                                        MT_WF_PHY_B0_PD_OFDM_MASK,
-                                        MT_WF_PHY_B0_PD_OFDM(val));
-                       else
-                               mt76_rmw(dev, MT_WF_PHY_B1_MIN_PRI_PWR,
-                                        MT_WF_PHY_B1_PD_OFDM_MASK,
-                                        MT_WF_PHY_B1_PD_OFDM(val));
+                       mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
+                                MT_WF_PHY_PD_OFDM_MASK(ext_phy),
+                                MT_WF_PHY_PD_OFDM(ext_phy, val));
                } else {
                        val = *sensitivity + 256;
                        if (!ext_phy)
-                               mt76_rmw(dev, MT_WF_PHY_B0_RXTD_CCK_PD,
-                                        MT_WF_PHY_B0_PD_CCK_MASK,
-                                        MT_WF_PHY_B0_PD_CCK(val));
-                       else
-                               mt76_rmw(dev, MT_WF_PHY_B1_RXTD_CCK_PD,
-                                        MT_WF_PHY_B1_PD_CCK_MASK,
-                                        MT_WF_PHY_B1_PD_CCK(val));
+                       mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
+                                MT_WF_PHY_PD_CCK_MASK(ext_phy),
+                                MT_WF_PHY_PD_CCK(ext_phy, val));
                }
                phy->last_cca_adj = jiffies;
        }

diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/regs.h b/drivers/net/wireless/mediatek/mt76/mt7615/regs.h
index b0c14067a832e96abb7e872ca6dfb3ca9b1babe5..c42f3a47a2f143905d2b4789599212b7db69ea38 100644 (file)
--- a/drivers/net/wireless/mediatek/mt76/mt7615/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7615/regs.h
@@ -81,7 +81,7 @@
 #define MT_WF_PHY_BASE                 0x10000
 #define MT_WF_PHY(ofs)                 (MT_WF_PHY_BASE + (ofs))
 
-#define MT_WF_PHY_WF2_RFCTRL0(n)       MT_WF_PHY(0x1900 + ((n) * 0x400))
+#define MT_WF_PHY_WF2_RFCTRL0(n)       MT_WF_PHY(0x1900 + (n) * 0x400)
 #define MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN BIT(9)
 
 #define MT_WF_PHY_R0_PHYMUX_5(_phy)    MT_WF_PHY(0x0614 + ((_phy) << 9))
@@ -94,26 +94,19 @@
 #define MT_WF_PHYCTRL_STAT_MDRDY_OFDM  GENMASK(31, 16)
 #define MT_WF_PHYCTRL_STAT_MDRDY_CCK   GENMASK(15, 0)
 
-#define MT_WF_PHY_B0_MIN_PRI_PWR       MT_WF_PHY(0x229c)
-#define MT_WF_PHY_B0_PD_OFDM_MASK      GENMASK(28, 20)
-#define MT_WF_PHY_B0_PD_OFDM(v)                ((v) << 20)
-#define MT_WF_PHY_B0_PD_BLK            BIT(19)
-
-#define MT_WF_PHY_B1_MIN_PRI_PWR       MT_WF_PHY(0x084)
-#define MT_WF_PHY_B1_PD_OFDM_MASK      GENMASK(24, 16)
-#define MT_WF_PHY_B1_PD_OFDM(v)                ((v) << 16)
-#define MT_WF_PHY_B1_PD_BLK            BIT(25)
+#define MT_WF_PHY_MIN_PRI_PWR(_phy)    MT_WF_PHY((_phy) ? 0x084 : 0x229c)
+#define MT_WF_PHY_PD_OFDM_MASK(_phy)   ((_phy) ? GENMASK(24, 16) : \
+                                        GENMASK(28, 20))
+#define MT_WF_PHY_PD_OFDM(_phy, v)     ((v) << ((_phy) ? 16 : 20))
+#define MT_WF_PHY_PD_BLK(_phy)         ((_phy) ? BIT(25) : BIT(19))
 
 #define MT_WF_PHY_RXTD_BASE            MT_WF_PHY(0x2200)
 #define MT_WF_PHY_RXTD(_n)             (MT_WF_PHY_RXTD_BASE + ((_n) << 2))
 
-#define MT_WF_PHY_B0_RXTD_CCK_PD       MT_WF_PHY(0x2310)
-#define MT_WF_PHY_B0_PD_CCK_MASK       GENMASK(8, 1)
-#define MT_WF_PHY_B0_PD_CCK(v)         ((v) << 1)
-
-#define MT_WF_PHY_B1_RXTD_CCK_PD       MT_WF_PHY(0x2314)
-#define MT_WF_PHY_B1_PD_CCK_MASK       GENMASK(31, 24)
-#define MT_WF_PHY_B1_PD_CCK(v)         ((v) << 24)
+#define MT_WF_PHY_RXTD_CCK_PD(_phy)    MT_WF_PHY((_phy) ? 0x2314 : 0x2310)
+#define MT_WF_PHY_PD_CCK_MASK(_phy)    (_phy) ? GENMASK(31, 24) : \
+                                        GENMASK(8, 1)
+#define MT_WF_PHY_PD_CCK(_phy, v)      ((v) << ((_phy) ? 24 : 1))
 
 #define MT_WF_PHY_RXTD2_BASE           MT_WF_PHY(0x2a00)
 #define MT_WF_PHY_RXTD2(_n)            (MT_WF_PHY_RXTD2_BASE + ((_n) << 2))
@@ -127,15 +120,6 @@
 #define MT_CFG_CCR_MAC_D1_2X_GC_EN     BIT(30)
 #define MT_CFG_CCR_MAC_D0_2X_GC_EN     BIT(31)
 
-#define MT_DBDC_CTRL0                  MT_WF_CFG(0x050)
-#define MT_DBDC_CTRL0_OMAC_00_04       GENMASK(4, 0)
-#define MT_DBDC_CTRL0_OMAC_11_1F       GENMASK(19, 5)
-#define MT_DBDC_CTRL0_MGMT             GENMASK(21, 20)
-#define MT_DBDC_CTRL0_WMM              GENMASK(25, 22)
-#define MT_DBDC_CTRL0_DBDC_EN          BIT(31)
-
-#define MT_DBDC_CTRL1                  MT_WF_CFG(0x054)
-
 #define MT_WF_AGG_BASE                 0x20a00
 #define MT_WF_AGG(ofs)                 (MT_WF_AGG_BASE + (ofs))
 
@@ -146,8 +130,8 @@
 #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19)
 #define MT_AGG_ARCR_RATE_UP_EXTRA_TH   GENMASK(22, 20)
 
-#define MT_AGG_ARUCR                   MT_WF_AGG(0x018)
-#define MT_AGG_ARDCR                   MT_WF_AGG(0x01c)
+#define MT_AGG_ARUCR(_band)            MT_WF_AGG(0x018 + (_band) * 0x100)
+#define MT_AGG_ARDCR(_band)            MT_WF_AGG(0x01c + (_band) * 0x100)
 #define MT_AGG_ARxCR_LIMIT_SHIFT(_n)   (4 * (_n))
 #define MT_AGG_ARxCR_LIMIT(_n)         GENMASK(2 + \
                                        MT_AGG_ARxCR_LIMIT_SHIFT(_n), \
@@ -157,8 +141,7 @@
 #define MT_AGG_ASRCR1                  MT_WF_AGG(0x064)
 #define MT_AGG_ASRCR_RANGE(val, n)     (((val) >> ((n) << 3)) & GENMASK(5, 0))
 
-#define MT_AGG_ACR0                    MT_WF_AGG(0x070)
-#define MT_AGG_ACR1                    MT_WF_AGG(0x170)
+#define MT_AGG_ACR(_band)              MT_WF_AGG(0x070 + (_band) * 0x100)
 #define MT_AGG_ACR_NO_BA_RULE          BIT(0)
 #define MT_AGG_ACR_NO_BA_AR_RULE       BIT(1)
 #define MT_AGG_ACR_PKT_TIME_EN         BIT(2)
@@ -185,13 +168,11 @@
 #define MT_TIMEOUT_VAL_PLCP            GENMASK(15, 0)
 #define MT_TIMEOUT_VAL_CCA             GENMASK(31, 16)
 
-#define MT_TMAC_TRCR0                  MT_WF_TMAC(0x09c)
-#define MT_TMAC_TRCR1                  MT_WF_TMAC(0x070)
+#define MT_TMAC_TRCR(_band)            MT_WF_TMAC((_band) ? 0x070 : 0x09c)
 #define MT_TMAC_TRCR_CCA_SEL           GENMASK(31, 30)
 #define MT_TMAC_TRCR_SEC_CCA_SEL       GENMASK(29, 28)
 
-#define MT_TMAC_ICR0                   MT_WF_TMAC(0x0a4)
-#define MT_TMAC_ICR1                   MT_WF_TMAC(0x074)
+#define MT_TMAC_ICR(_band)             MT_WF_TMAC((_band) ? 0x074 : 0x0a4)
 #define MT_IFS_EIFS                    GENMASK(8, 0)
 #define MT_IFS_RIFS                    GENMASK(14, 10)
 #define MT_IFS_SIFS                    GENMASK(22, 16)
@@ -255,8 +236,7 @@
 #define MT_DMA_DCR0_MAX_RX_LEN         GENMASK(15, 2)
 #define MT_DMA_DCR0_RX_VEC_DROP                BIT(17)
 
-#define MT_DMA_BN0RCFR0                        MT_WF_DMA(0x070)
-#define MT_DMA_BN1RCFR0                        MT_WF_DMA(0x0b0)
+#define MT_DMA_RCFR0(_band)            MT_WF_DMA(0x070 + (_band) * 0x40)
 #define MT_DMA_RCFR0_MCU_RX_MGMT       BIT(2)
 #define MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR        BIT(3)
 #define MT_DMA_RCFR0_MCU_RX_CTL_BAR    BIT(4)