#define HZIP_SGL_SGE_NR                                10
 
 static const u8 zlib_head[HZIP_ZLIB_HEAD_SIZE] = {0x78, 0x9c};
-static const u8 gzip_head[HZIP_GZIP_HEAD_SIZE] = {0x1f, 0x8b, 0x08, 0x0, 0x0,
-                                                 0x0, 0x0, 0x0, 0x0, 0x03};
+static const u8 gzip_head[HZIP_GZIP_HEAD_SIZE] = {
+       0x1f, 0x8b, 0x08, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x03
+};
+
 enum hisi_zip_alg_type {
        HZIP_ALG_TYPE_COMP = 0,
        HZIP_ALG_TYPE_DECOMP = 1,
 
        atomic64_inc(&dfx->recv_cnt);
        status = sqe->dw3 & HZIP_BD_STATUS_M;
-
        if (status != 0 && status != HZIP_NC_ERR) {
                dev_err(dev, "%scompress fail in qp%u: %u, output: %u\n",
                        (qp->alg_type == 0) ? "" : "de", qp->qp_id, status,
        struct hisi_acc_sgl_pool *pool = qp_ctx->sgl_pool;
        struct hisi_zip_dfx *dfx = &qp_ctx->zip_dev->dfx;
        struct hisi_zip_sqe zip_sqe;
-       dma_addr_t input;
-       dma_addr_t output;
+       dma_addr_t input, output;
        int ret;
 
        if (!a_req->src || !a_req->slen || !a_req->dst || !a_req->dlen)
                                                    (req->req_id << 1) + 1,
                                                    &output);
        if (IS_ERR(req->hw_dst)) {
-               dev_err(dev, "failed to map the dst buffer to hw slg (%ld)!\n",
-                       PTR_ERR(req->hw_dst));
                ret = PTR_ERR(req->hw_dst);
+               dev_err(dev, "failed to map the dst buffer to hw slg (%d)!\n",
+                       ret);
                goto err_unmap_input;
        }
        req->dma_dst = output;
 
        /* qm cache */
        writel(AXI_M_CFG, base + QM_AXI_M_CFG);
        writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE);
+
        /* disable FLR triggered by BME(bus master enable) */
        writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG);
        writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE);
        writel(0x1, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
        writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
        writel(HZIP_CORE_INT_RAS_NFE_ENABLE,
-               qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
+              qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
 
        /* enable ZIP hw error interrupts */
        writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
        .write = hisi_zip_ctrl_debug_write,
 };
 
-
 static int zip_debugfs_atomic64_set(void *data, u64 val)
 {
        if (val)
        while (err->msg) {
                if (err->int_msk & err_sts) {
                        dev_err(dev, "%s [error status=0x%x] found\n",
-                                err->msg, err->int_msk);
+                               err->msg, err->int_msk);
 
                        if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) {
                                err_val = readl(qm->io_base +
                                dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n",
                                        ((err_val >>
                                        HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF));
-                               dev_err(dev, "hisi-zip multi ecc sram addr=0x%x\n",
-                                       (err_val >>
-                                       HZIP_SRAM_ECC_ERR_ADDR_SHIFT));
                        }
                }
                err++;
 
        ret = pci_register_driver(&hisi_zip_pci_driver);
        if (ret < 0) {
+               hisi_zip_unregister_debugfs();
                pr_err("Failed to register pci driver.\n");
-               goto err_pci;
        }
 
-       return 0;
-
-err_pci:
-       hisi_zip_unregister_debugfs();
-
        return ret;
 }