drm/amdgpu: Show deferred error count for UMC

Show deferred error count for UMC syfs node

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index bf08a7744a4af2f3c6a3029bf236bb8682eb8054..850cad69e4b72dd9d44eaa8d0fec3595699fe7a1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -632,8 +632,12 @@ static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
                        dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
        }
 
-       return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
-                         "ce", info.ce_count);
+       if (info.head.block == AMDGPU_RAS_BLOCK__UMC)
+               return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count,
+                               "ce", info.ce_count, "de", info.de_count);
+       else
+               return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
+                               "ce", info.ce_count);
 }
 
 /* obj begin */