items:
        - const: irq
  
 +  connector:
 +    $ref: /schemas/connector/usb-connector.yaml#
 +
+   firmware-name:
+     description: |
+       Should contain the name of the default patch binary
+       file located on the firmware search path which is
+       used to switch the controller into APP mode.
+       This is used when tps25750 doesn't have an EEPROM
+       connected to it.
+     maxItems: 1
+ 
  required:
    - compatible
    - reg
  
 -additionalProperties: true
+ allOf:
+   - if:
+       properties:
+         compatible:
+           contains:
+             const: ti,tps25750
+     then:
+       properties:
+         reg:
+           maxItems: 2
+ 
+         connector:
+           required:
+             - data-role
+ 
+       required:
+         - connector
+         - reg-names
+     else:
+       properties:
+         reg:
+           maxItems: 1
+ 
 +additionalProperties: false
  
  examples:
    - |
 
                status = "disabled";
        };
  
+       usb_host2_xhci: usb@fcd00000 {
+               compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+               reg = <0x0 0xfcd00000 0x0 0x400000>;
+               interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
+                        <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
+                        <&cru CLK_PIPEPHY2_PIPE_U3_G>;
+               clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
+               dr_mode = "host";
+               phys = <&combphy2_psu PHY_TYPE_USB3>;
+               phy-names = "usb3-phy";
+               phy_type = "utmi_wide";
+               resets = <&cru SRST_A_USB3OTG2>;
+               snps,dis_enblslpm_quirk;
+               snps,dis-u2-freeclk-exists-quirk;
+               snps,dis-del-phy-power-chg-quirk;
+               snps,dis-tx-ipgap-linecheck-quirk;
+               snps,dis_rxdet_inp3_quirk;
+               status = "disabled";
+       };
+ 
 +      pmu1grf: syscon@fd58a000 {
 +              compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
 +              reg = <0x0 0xfd58a000 0x0 0x10000>;
 +      };
 +
        sys_grf: syscon@fd58c000 {
                compatible = "rockchip,rk3588-sys-grf", "syscon";
                reg = <0x0 0xfd58c000 0x0 0x1000>;
 
  struct urb_priv {
        int     num_tds;
        int     num_tds_done;
 -      struct  xhci_td td[];
 +      struct  xhci_td td[] __counted_by(num_tds);
  };
  
- /*
-  * Each segment table entry is 4*32bits long.  1K seems like an ok size:
-  * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
-  * meaning 64 ring segments.
-  * Initial allocated size of the ERST, in number of entries */
- #define       ERST_NUM_SEGS   1
+ /* Reasonable limit for number of Event Ring segments (spec allows 32k) */
+ #define       ERST_MAX_SEGS   2
  /* Poll every 60 seconds */
  #define       POLL_TIMEOUT    60
  /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */