CS42L42_CLK_OASRC_SEL_MASK,
                                        CS42L42_CLK_OASRC_SEL_12 <<
                                        CS42L42_CLK_OASRC_SEL_SHIFT);
-                       /* channel 1 on low LRCLK, 32 bit */
-                       snd_soc_component_update_bits(component,
-                                       CS42L42_ASP_RX_DAI0_CH1_AP_RES,
-                                       CS42L42_ASP_RX_CH_AP_MASK |
-                                       CS42L42_ASP_RX_CH_RES_MASK,
-                                       (CS42L42_ASP_RX_CH_AP_LOW <<
-                                       CS42L42_ASP_RX_CH_AP_SHIFT) |
-                                       (CS42L42_ASP_RX_CH_RES_32 <<
-                                       CS42L42_ASP_RX_CH_RES_SHIFT));
-                       /* Channel 2 on high LRCLK, 32 bit */
-                       snd_soc_component_update_bits(component,
-                                       CS42L42_ASP_RX_DAI0_CH2_AP_RES,
-                                       CS42L42_ASP_RX_CH_AP_MASK |
-                                       CS42L42_ASP_RX_CH_RES_MASK,
-                                       (CS42L42_ASP_RX_CH_AP_HI <<
-                                       CS42L42_ASP_RX_CH_AP_SHIFT) |
-                                       (CS42L42_ASP_RX_CH_RES_32 <<
-                                       CS42L42_ASP_RX_CH_RES_SHIFT));
                        if (pll_ratio_table[i].mclk_src_sel == 0) {
                                /* Pass the clock straight through */
                                snd_soc_component_update_bits(component,
 {
        struct snd_soc_component *component = dai->component;
        struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
-       int retval;
+       unsigned int width = (params_width(params) / 8) - 1;
+       unsigned int val = 0;
 
        cs42l42->srate = params_rate(params);
-       cs42l42->swidth = params_width(params);
 
-       retval = cs42l42_pll_config(component);
+       switch(substream->stream) {
+       case SNDRV_PCM_STREAM_PLAYBACK:
+               val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
+               /* channel 1 on low LRCLK */
+               snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
+                                                        CS42L42_ASP_RX_CH_AP_MASK |
+                                                        CS42L42_ASP_RX_CH_RES_MASK, val);
+               /* Channel 2 on high LRCLK */
+               val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
+               snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
+                                                        CS42L42_ASP_RX_CH_AP_MASK |
+                                                        CS42L42_ASP_RX_CH_RES_MASK, val);
+               break;
+       default:
+               break;
+       }
 
-       return retval;
+       return cs42l42_pll_config(component);
 }
 
 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
        return 0;
 }
 
-#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
-                       SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
-                       SNDRV_PCM_FMTBIT_S32_LE)
+#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+                        SNDRV_PCM_FMTBIT_S24_LE |\
+                        SNDRV_PCM_FMTBIT_S32_LE )
 
 
 static const struct snd_soc_dai_ops cs42l42_ops = {