Some clock muxes have holes, i.e. invalid or unconnected inputs,
between parent mux values.
Add support for specifying a mux table to map clock parents to
mux values.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
        parent = reg >> cm->shift;
        parent &= (1 << cm->width) - 1;
 
+       if (cm->table) {
+               int num_parents = clk_hw_get_num_parents(&common->hw);
+               int i;
+
+               for (i = 0; i < num_parents; i++)
+                       if (cm->table[i] == parent)
+                               return i;
+       }
+
        return parent;
 }
 
        unsigned long flags;
        u32 reg;
 
+       if (cm->table)
+               index = cm->table[index];
+
        spin_lock_irqsave(common->lock, flags);
 
        reg = readl(common->base + common->reg);
 
 #include "ccu_common.h"
 
 struct ccu_mux_internal {
-       u8      shift;
-       u8      width;
+       u8              shift;
+       u8              width;
+       const u8        *table;
 
        struct {
                u8      index;
        } variable_prediv;
 };
 
-#define _SUNXI_CCU_MUX(_shift, _width)         \
-       {                                       \
-               .shift  = _shift,               \
-               .width  = _width,               \
+#define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table)   \
+       {                                               \
+               .shift  = _shift,                       \
+               .width  = _width,                       \
+               .table  = _table,                       \
        }
 
+#define _SUNXI_CCU_MUX(_shift, _width) \
+       _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
+
 struct ccu_mux {
        u16                     reg;
        u32                     enable;