drm/amd/powerplay: get raven max/min gfx clocks (v2)

v2: squash in rebase fix (Tom)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 6f0b2e5b68c79c2df7226bbcc41e131db5ee4fae..1ba69d65ed8b1b44504bb61f88c1b460ea993820 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -421,6 +421,26 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
        rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
                                        ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
 
+       PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
+                       PPSMC_MSG_GetMinGfxclkFrequency),
+                       "Attempt to get min GFXCLK Failed!",
+                       return -1);
+       PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
+                       &result),
+                       "Attempt to get min GFXCLK Failed!",
+                       return -1);
+       rv_data->gfx_min_freq_limit = result * 100;
+
+       PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
+                       PPSMC_MSG_GetMaxGfxclkFrequency),
+                       "Attempt to get max GFXCLK Failed!",
+                       return -1);
+       PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
+                       &result),
+                       "Attempt to get max GFXCLK Failed!",
+                       return -1);
+       rv_data->gfx_max_freq_limit = result * 100;
+
        return 0;
 }
 

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index 68d61bd95ca00794a2fa7c20dcce61e9a1a0ac81..9dc50305539468929663f5887d000ba9ae5521ef 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -283,6 +283,8 @@ struct rv_hwmgr {
        uint32_t                        vclk_soft_min;
        uint32_t                        dclk_soft_min;
        uint32_t                        gfx_actual_soft_min_freq;
+       uint32_t                        gfx_min_freq_limit;
+       uint32_t                        gfx_max_freq_limit;
 
        bool                           vcn_power_gated;
        bool                           vcn_dpg_mode;