arm64: dts: add imx8mp-libra-rdk-fpsc LVDS panel overlay

The Libra board has an LVDS connector. Add an overlay for an
etml1010g3dra LVDS panel supported for the phyCORE-i.MX 8M Plus that may
be connected to it.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 4ec67b438e8239db1def2ef2e5ec41f79a4e56f2..d63000efdf2770f107a48cb87aa81390fac2b4c4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -210,6 +210,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb
 
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb
+imx8mp-libra-rdk-fpsc-lvds-dtbs += imx8mp-libra-rdk-fpsc.dtb imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso
new file mode 100644 (file)
index 0000000..1dcf249
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+/dts-v1/;
+/plugin/;
+
+&backlight_lvds0 {
+       brightness-levels = <0 8 16 32 64 128 255>;
+       default-brightness-level = <8>;
+       enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
+       num-interpolated-steps = <2>;
+       pwms = <&pwm1 0 66667 0>;
+       status = "okay";
+};
+
+&lcdif2 {
+       status = "okay";
+};
+
+&lvds_bridge {
+       assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
+       assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+       /*
+        * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
+        * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout
+        * engine can reach accurate pixel clock of exactly 72.4 MHz.
+        */
+       assigned-clock-rates = <0>, <506800000>;
+       status = "okay";
+};
+
+&panel0_lvds {
+       compatible = "edt,etml1010g3dra";
+       status = "okay";
+};
+
+&pwm1 {
+       status = "okay";
+};