#define QUADSPI_IPCR                  0x08
  #define QUADSPI_IPCR_SEQID(x)         ((x) << 24)
  
+ #define QUADSPI_FLSHCR                        0x0c
+ #define QUADSPI_FLSHCR_TCSS_MASK      GENMASK(3, 0)
+ #define QUADSPI_FLSHCR_TCSH_MASK      GENMASK(11, 8)
+ #define QUADSPI_FLSHCR_TDH_MASK               GENMASK(17, 16)
+ 
 +#define QUADSPI_BUF0CR                  0x10
 +#define QUADSPI_BUF1CR                  0x14
 +#define QUADSPI_BUF2CR                  0x18
 +#define QUADSPI_BUFXCR_INVALID_MSTRID   0xe
 +
  #define QUADSPI_BUF3CR                        0x1c
  #define QUADSPI_BUF3CR_ALLMST_MASK    BIT(31)
  #define QUADSPI_BUF3CR_ADATSZ(x)      ((x) << 8)
  static const struct fsl_qspi_devtype_data imx7d_data = {
        .rxfifo = SZ_128,
        .txfifo = SZ_512,
 +      .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
        .ahb_buf_size = SZ_1K,
-       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
+                 QUADSPI_QUIRK_USE_TDH_SETTING,
        .little_endian = true,
  };
  
  static const struct fsl_qspi_devtype_data imx6ul_data = {
        .rxfifo = SZ_128,
        .txfifo = SZ_512,
 +      .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
        .ahb_buf_size = SZ_1K,
-       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
+                 QUADSPI_QUIRK_USE_TDH_SETTING,
        .little_endian = true,
  };
  
 
                return -ENOMEM;
  
        status = devm_add_action_or_reset(&pdev->dev, spi_gpio_put, master);
-       if (status)
+       if (status) {
+               spi_master_put(master);
                return status;
+       }
  
 -      if (of_id)
 +      if (pdev->dev.of_node)
                status = spi_gpio_probe_dt(pdev, master);
        else
                status = spi_gpio_probe_pdata(pdev, master);