cpufreq: qcom-nvmem: Enable cpufreq for ipq5424

IPQ5424 have different OPPs available for the CPU based on
SoC variant. This can be determined through use of an eFuse
register present in the silicon.

Added support for ipq5424 on nvmem driver which helps to
determine OPPs at runtime based on the eFuse register which
has the CPU frequency limits. opp-supported-hw dt binding
can be used to indicate the available OPPs for each limit.

nvmem driver also creates the "cpufreq-dt" platform_device after
passing the version matching data to the OPP framework so that the
cpufreq-dt handles the actual cpufreq implementation.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
[ Changed '!=' based check to '==' based check ]
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 0f954b07dcb35207bfa83f883ff8ef445f98794e..1a9d9d008002cac31b07699123fdd22220c656e8 100644 (file)
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -192,6 +192,7 @@ static const struct of_device_id blocklist[] __initconst = {
        { .compatible = "ti,am62p5", },
 
        { .compatible = "qcom,ipq5332", },
+       { .compatible = "qcom,ipq5424", },
        { .compatible = "qcom,ipq6018", },
        { .compatible = "qcom,ipq8064", },
        { .compatible = "qcom,ipq8074", },

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 54f8117103c850ff8a7d1a8cd408b7117939cb0d..765a5bb81829e1bbd584fd7e30139966c911f104 100644 (file)
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -200,6 +200,10 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
        case QCOM_ID_IPQ9574:
                drv->versions = 1 << (unsigned int)(*speedbin);
                break;
+       case QCOM_ID_IPQ5424:
+       case QCOM_ID_IPQ5404:
+               drv->versions = (*speedbin == 0x3b) ? BIT(1) : BIT(0);
+               break;
        case QCOM_ID_MSM8996SG:
        case QCOM_ID_APQ8096SG:
                drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
@@ -591,6 +595,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst __maybe_u
        { .compatible = "qcom,msm8996", .data = &match_data_kryo },
        { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
        { .compatible = "qcom,ipq5332", .data = &match_data_kryo },
+       { .compatible = "qcom,ipq5424", .data = &match_data_kryo },
        { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
        { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
        { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },