drm/nouveau/disp/dp: gm1xx appears to have same dp lane ordering as gm2xx

Fixes 2-lane DP on Quadro K620.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
index b4ed620070fa885896ed1474e8f642e14ed2d2a2..b9dfa660e7dd00369cef63b03a7fcc8f859d7333 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
@@ -214,6 +214,7 @@ extern struct nvkm_output_dp_impl nv50_pior_dp_impl;
 extern struct nvkm_oclass *nv50_disp_outp_sclass[];
 
 extern struct nvkm_output_dp_impl g94_sor_dp_impl;
+u32 g94_sor_dp_lane_map(struct nv50_disp_priv *, u8 lane);
 int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
 extern struct nvkm_oclass *g94_disp_outp_sclass[];
 

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
index 2982ebf1affd1417f5f2e18d5e7f770a7a753f93..22443627a0862a11fdde0776269c345d1b3ef01b 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
@@ -39,11 +39,14 @@ g94_sor_loff(struct nvkm_output_dp *outp)
        return g94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
 }
 
-static inline u32
+u32
 g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
 {
+       static const u8 gm100[] = { 0, 8, 16, 24 };
        static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
-       static const u8 g94[] = { 16, 8, 0, 24 };
+       static const u8   g94[] = { 16, 8, 0, 24 };
+       if (nv_device(priv)->chipset >= 0x110)
+               return gm100[lane];
        if (nv_device(priv)->chipset == 0xaf)
                return mcp89[lane];
        return g94[lane];

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c
index 2107e314a1171423275c8fbbc547d25ec8b39b83..1f02b603e19a669c17de835e0b2038a09f1df1f4 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c
@@ -36,13 +36,6 @@ gf110_sor_loff(struct nvkm_output_dp *outp)
        return gf110_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
 }
 
-static inline u32
-gf110_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
-{
-       static const u8 gf110[] = { 16, 8, 0, 24 };
-       return gf110[lane];
-}
-
 static int
 gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 {
@@ -77,7 +70,7 @@ gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
 {
        struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
        struct nvkm_bios *bios = nvkm_bios(priv);
-       const u32 shift = gf110_sor_dp_lane_map(priv, ln);
+       const u32 shift = g94_sor_dp_lane_map(priv, ln);
        const u32 loff = gf110_sor_loff(outp);
        u32 addr, data[4];
        u8  ver, hdr, cnt, len;