crypto: caam - add support for i.MX8M Nano

Add support for the crypto engine used in i.mx8mn (i.MX 8M "Nano"),
which is very similar to the one used in i.mx8mq, i.mx8mm.

Since the clocks are identical for all members of i.MX 8M family,
simplify the SoC <--> clock array mapping table.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Tested-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 6659c8d9672eb66eeb63388a10af4b54dd04b632..88a58a8fc5332a9adfe7ca2a424c3c45f8943ce2 100644 (file)
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -99,11 +99,12 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
 
        if (ctrlpriv->virt_en == 1 ||
            /*
-            * Apparently on i.MX8MQ it doesn't matter if virt_en == 1
+            * Apparently on i.MX8MQ, 8MM, 8MN it doesn't matter if virt_en == 1
             * and the following steps should be performed regardless
             */
            of_machine_is_compatible("fsl,imx8mq") ||
-           of_machine_is_compatible("fsl,imx8mm")) {
+           of_machine_is_compatible("fsl,imx8mm") ||
+           of_machine_is_compatible("fsl,imx8mn")) {
                clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 
                while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
@@ -509,8 +510,7 @@ static const struct soc_device_attribute caam_imx_soc_table[] = {
        { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
        { .soc_id = "i.MX6*",  .data = &caam_imx6_data },
        { .soc_id = "i.MX7*",  .data = &caam_imx7_data },
-       { .soc_id = "i.MX8MQ", .data = &caam_imx7_data },
-       { .soc_id = "i.MX8MM", .data = &caam_imx7_data },
+       { .soc_id = "i.MX8M*", .data = &caam_imx7_data },
        { .family = "Freescale i.MX" },
        { /* sentinel */ }
 };