phy: exynos5-usbdrd: uniform order of register bit macros

Most of the macros are ordered high -> low, but there are some
outliers.

Order them all uniformly from high to low. This will allow adding
additional register (field) definitions in a consistent way.

While at it, also remove some extra empty lines to group register bit
field definitions together with the relevant register. This makes the
registers easier to distinguish visually.

No functional change.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-1-4ccba5afa7cc@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 04171eed5b16fbd930a1b3a7a65ac96a4de5c12d..2af192c15d789c87c1d2db7bbcc2fceabee61c8a 100644 (file)
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -35,13 +35,11 @@
 
 /* Exynos5: USB 3.0 DRD PHY registers */
 #define EXYNOS5_DRD_LINKSYSTEM                 0x04
-
+#define LINKSYSTEM_XHCI_VERSION_CONTROL                BIT(27)
 #define LINKSYSTEM_FLADJ_MASK                  (0x3f << 1)
 #define LINKSYSTEM_FLADJ(_x)                   ((_x) << 1)
-#define LINKSYSTEM_XHCI_VERSION_CONTROL                BIT(27)
 
 #define EXYNOS5_DRD_PHYUTMI                    0x08
-
 #define PHYUTMI_OTGDISABLE                     BIT(6)
 #define PHYUTMI_FORCESUSPEND                   BIT(1)
 #define PHYUTMI_FORCESLEEP                     BIT(0)
@@ -49,40 +47,31 @@
 #define EXYNOS5_DRD_PHYPIPE                    0x0c
 
 #define EXYNOS5_DRD_PHYCLKRST                  0x10
-
 #define PHYCLKRST_EN_UTMISUSPEND               BIT(31)
-
 #define PHYCLKRST_SSC_REFCLKSEL_MASK           (0xff << 23)
 #define PHYCLKRST_SSC_REFCLKSEL(_x)            ((_x) << 23)
-
 #define PHYCLKRST_SSC_RANGE_MASK               (0x03 << 21)
 #define PHYCLKRST_SSC_RANGE(_x)                        ((_x) << 21)
-
 #define PHYCLKRST_SSC_EN                       BIT(20)
 #define PHYCLKRST_REF_SSP_EN                   BIT(19)
 #define PHYCLKRST_REF_CLKDIV2                  BIT(18)
-
 #define PHYCLKRST_MPLL_MULTIPLIER_MASK         (0x7f << 11)
 #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF   (0x19 << 11)
 #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF      (0x32 << 11)
 #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF    (0x68 << 11)
 #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF    (0x7d << 11)
 #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
-
-#define PHYCLKRST_FSEL_UTMI_MASK               (0x7 << 5)
 #define PHYCLKRST_FSEL_PIPE_MASK               (0x7 << 8)
+#define PHYCLKRST_FSEL_UTMI_MASK               (0x7 << 5)
 #define PHYCLKRST_FSEL(_x)                     ((_x) << 5)
 #define PHYCLKRST_FSEL_PAD_100MHZ              (0x27 << 5)
 #define PHYCLKRST_FSEL_PAD_24MHZ               (0x2a << 5)
 #define PHYCLKRST_FSEL_PAD_20MHZ               (0x31 << 5)
 #define PHYCLKRST_FSEL_PAD_19_2MHZ             (0x38 << 5)
-
 #define PHYCLKRST_RETENABLEN                   BIT(4)
-
 #define PHYCLKRST_REFCLKSEL_MASK               (0x03 << 2)
 #define PHYCLKRST_REFCLKSEL_PAD_REFCLK         (0x2 << 2)
 #define PHYCLKRST_REFCLKSEL_EXT_REFCLK         (0x3 << 2)
-
 #define PHYCLKRST_PORTRESET                    BIT(1)
 #define PHYCLKRST_COMMONONN                    BIT(0)
 
@@ -100,30 +89,27 @@
 #define PHYREG1_CR_ACK                         BIT(0)
 
 #define EXYNOS5_DRD_PHYPARAM0                  0x1c
-
 #define PHYPARAM0_REF_USE_PAD                  BIT(31)
 #define PHYPARAM0_REF_LOSLEVEL_MASK            (0x1f << 26)
 #define PHYPARAM0_REF_LOSLEVEL                 (0x9 << 26)
 
 #define EXYNOS5_DRD_PHYPARAM1                  0x20
-
 #define PHYPARAM1_PCS_TXDEEMPH_MASK            (0x1f << 0)
 #define PHYPARAM1_PCS_TXDEEMPH                 (0x1c)
 
 #define EXYNOS5_DRD_PHYTERM                    0x24
 
 #define EXYNOS5_DRD_PHYTEST                    0x28
-
 #define PHYTEST_POWERDOWN_SSP                  BIT(3)
 #define PHYTEST_POWERDOWN_HSP                  BIT(2)
 
 #define EXYNOS5_DRD_PHYADP                     0x2c
 
 #define EXYNOS5_DRD_PHYUTMICLKSEL              0x30
-
 #define PHYUTMICLKSEL_UTMI_CLKSEL              BIT(2)
 
 #define EXYNOS5_DRD_PHYRESUME                  0x34
+
 #define EXYNOS5_DRD_LINKPORT                   0x44
 
 /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
@@ -147,28 +133,28 @@
 
 /* Exynos850: USB DRD PHY registers */
 #define EXYNOS850_DRD_LINKCTRL                 0x04
-#define LINKCTRL_BUS_FILTER_BYPASS(_x)         ((_x) << 4)
 #define LINKCTRL_FORCE_QACT                    BIT(8)
+#define LINKCTRL_BUS_FILTER_BYPASS(_x)         ((_x) << 4)
 
 #define EXYNOS850_DRD_CLKRST                   0x20
-#define CLKRST_LINK_SW_RST                     BIT(0)
-#define CLKRST_PORT_RST                                BIT(1)
 #define CLKRST_PHY_SW_RST                      BIT(3)
+#define CLKRST_PORT_RST                                BIT(1)
+#define CLKRST_LINK_SW_RST                     BIT(0)
 
 #define EXYNOS850_DRD_UTMI                     0x50
-#define UTMI_FORCE_SLEEP                       BIT(0)
-#define UTMI_FORCE_SUSPEND                     BIT(1)
-#define UTMI_DM_PULLDOWN                       BIT(2)
-#define UTMI_DP_PULLDOWN                       BIT(3)
-#define UTMI_FORCE_BVALID                      BIT(4)
 #define UTMI_FORCE_VBUSVALID                   BIT(5)
+#define UTMI_FORCE_BVALID                      BIT(4)
+#define UTMI_DP_PULLDOWN                       BIT(3)
+#define UTMI_DM_PULLDOWN                       BIT(2)
+#define UTMI_FORCE_SUSPEND                     BIT(1)
+#define UTMI_FORCE_SLEEP                       BIT(0)
 
 #define EXYNOS850_DRD_HSP                      0x54
-#define HSP_COMMONONN                          BIT(8)
-#define HSP_EN_UTMISUSPEND                     BIT(9)
-#define HSP_VBUSVLDEXT                         BIT(12)
-#define HSP_VBUSVLDEXTSEL                      BIT(13)
 #define HSP_FSV_OUT_EN                         BIT(24)
+#define HSP_VBUSVLDEXTSEL                      BIT(13)
+#define HSP_VBUSVLDEXT                         BIT(12)
+#define HSP_EN_UTMISUSPEND                     BIT(9)
+#define HSP_COMMONONN                          BIT(8)
 
 #define EXYNOS850_DRD_HSP_TEST                 0x5c
 #define HSP_TEST_SIDDQ                         BIT(24)