drm/amd/display: clear mpc_tree in init_pipes

[Why]
During init_pipes, otg master is not initialized. So mpc tree is
still configured even if mpc bottom is not active

[How]
For pipes that have tg enabled, check their mpc tree and clear
opp_list if mpc bottom is not active

Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Samson Tam <samson.tam@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 314798400b16e93f60769e0176bba1ab8fbf2b04..e0c3c14d12f3e1c2884cce201e9ef9dd7887ab59 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1366,6 +1366,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
        struct dce_hwseq *hws = dc->hwseq;
        struct hubbub *hubbub = dc->res_pool->hubbub;
        bool can_apply_seamless_boot = false;
+       bool tg_enabled[MAX_PIPES] = {false};
 
        for (i = 0; i < context->stream_count; i++) {
                if (context->streams[i]->apply_seamless_boot_optimization) {
@@ -1447,6 +1448,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
                        // requesting data while in PSR.
                        tg->funcs->tg_init(tg);
                        hubp->power_gated = true;
+                       tg_enabled[i] = true;
                        continue;
                }
 
@@ -1488,6 +1490,20 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
                tg->funcs->tg_init(tg);
        }
 
+       /* Clean up MPC tree */
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               if (tg_enabled[i]) {
+                       if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) {
+                               if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) {
+                                       int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id;
+
+                                       if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))
+                                               dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
+                               }
+                       }
+               }
+       }
+
        /* Power gate DSCs */
        if (hws->funcs.dsc_pg_control != NULL) {
                uint32_t num_opps = 0;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 56b0b6edbee020c15d4c97899b40ea52d3d84611..2fb90c2330a8b9ed446736d5a121a95d69f9a47b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -720,6 +720,7 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)
        struct hubbub *hubbub = dc->res_pool->hubbub;
        struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
        bool can_apply_seamless_boot = false;
+       bool tg_enabled[MAX_PIPES] = {false};
 
        for (i = 0; i < context->stream_count; i++) {
                if (context->streams[i]->apply_seamless_boot_optimization) {
@@ -801,6 +802,7 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)
                        // requesting data while in PSR.
                        tg->funcs->tg_init(tg);
                        hubp->power_gated = true;
+                       tg_enabled[i] = true;
                        continue;
                }
 
@@ -842,6 +844,20 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)
                tg->funcs->tg_init(tg);
        }
 
+       /* Clean up MPC tree */
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               if (tg_enabled[i]) {
+                       if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) {
+                               if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) {
+                                       int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id;
+
+                                       if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))
+                                               dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
+                               }
+                       }
+               }
+       }
+
        if (pg_cntl != NULL) {
                if (pg_cntl->funcs->dsc_pg_control != NULL) {
                        uint32_t num_opps = 0;