PCI: qcom: Add missing ipq806x clocks in PCIe driver

[ Upstream commit 8b6f0330b5f9a7543356bfa9e76d580f03aa2c1e ]

Aux and Ref clk are missing in PCIe qcom driver. Add support for this
optional clks for ipq8064/apq8064 SoC.

Link: https://lore.kernel.org/r/20200615210608.21469-2-ansuelsmth@gmail.com
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 270d502b8cd50cbce710ea8810e0862435f41f79..380a77a914fa0761c62b4916ac279b2f4b4250a6 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -103,6 +103,8 @@ struct qcom_pcie_resources_2_1_0 {
        struct clk *iface_clk;
        struct clk *core_clk;
        struct clk *phy_clk;
+       struct clk *aux_clk;
+       struct clk *ref_clk;
        struct reset_control *pci_reset;
        struct reset_control *axi_reset;
        struct reset_control *ahb_reset;
@@ -253,6 +255,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
        if (IS_ERR(res->phy_clk))
                return PTR_ERR(res->phy_clk);
 
+       res->aux_clk = devm_clk_get_optional(dev, "aux");
+       if (IS_ERR(res->aux_clk))
+               return PTR_ERR(res->aux_clk);
+
+       res->ref_clk = devm_clk_get_optional(dev, "ref");
+       if (IS_ERR(res->ref_clk))
+               return PTR_ERR(res->ref_clk);
+
        res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
        if (IS_ERR(res->pci_reset))
                return PTR_ERR(res->pci_reset);
@@ -285,6 +295,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
        clk_disable_unprepare(res->iface_clk);
        clk_disable_unprepare(res->core_clk);
        clk_disable_unprepare(res->phy_clk);
+       clk_disable_unprepare(res->aux_clk);
+       clk_disable_unprepare(res->ref_clk);
        regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
 }
 
@@ -315,16 +327,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
                goto err_assert_ahb;
        }
 
+       ret = clk_prepare_enable(res->core_clk);
+       if (ret) {
+               dev_err(dev, "cannot prepare/enable core clock\n");
+               goto err_clk_core;
+       }
+
        ret = clk_prepare_enable(res->phy_clk);
        if (ret) {
                dev_err(dev, "cannot prepare/enable phy clock\n");
                goto err_clk_phy;
        }
 
-       ret = clk_prepare_enable(res->core_clk);
+       ret = clk_prepare_enable(res->aux_clk);
        if (ret) {
-               dev_err(dev, "cannot prepare/enable core clock\n");
-               goto err_clk_core;
+               dev_err(dev, "cannot prepare/enable aux clock\n");
+               goto err_clk_aux;
+       }
+
+       ret = clk_prepare_enable(res->ref_clk);
+       if (ret) {
+               dev_err(dev, "cannot prepare/enable ref clock\n");
+               goto err_clk_ref;
        }
 
        ret = reset_control_deassert(res->ahb_reset);
@@ -400,10 +424,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
        return 0;
 
 err_deassert_ahb:
-       clk_disable_unprepare(res->core_clk);
-err_clk_core:
+       clk_disable_unprepare(res->ref_clk);
+err_clk_ref:
+       clk_disable_unprepare(res->aux_clk);
+err_clk_aux:
        clk_disable_unprepare(res->phy_clk);
 err_clk_phy:
+       clk_disable_unprepare(res->core_clk);
+err_clk_core:
        clk_disable_unprepare(res->iface_clk);
 err_assert_ahb:
        regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);