drm/amd/display: Block timing sync for different signals in PMO

PMO assumes that like timings can be synchronized, but DC only allows
this if the signal types match.

Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index 3bb5eb2e79aecb3f94df41e0debc3cb01c07a5df..d63558ee313519bc7ebef0cec26392c361a467c7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -941,7 +941,8 @@ static void build_synchronized_timing_groups(
                for (j = i + 1; j < display_config->display_config.num_streams; j++) {
                        if (memcmp(master_timing,
                                &display_config->display_config.stream_descriptors[j].timing,
-                               sizeof(struct dml2_timing_cfg)) == 0) {
+                               sizeof(struct dml2_timing_cfg)) == 0 &&
+                               display_config->display_config.stream_descriptors[i].output.output_encoder == display_config->display_config.stream_descriptors[j].output.output_encoder) {
                                set_bit_in_bitfield(&pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], j);
                                set_bit_in_bitfield(&stream_mapped_mask, j);
                        }