arm64: cpufeature: List early Cortex-A510 parts as having broken dbm

Versions of Cortex-A510 before r0p3 are affected by a hardware erratum
where the hardware update of the dirty bit is not correctly ordered.

Add these cpus to the cpu_has_broken_dbm list.

Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220125154040.549272-3-james.morse@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 1b0e53ececda923413c7118d5017e197ba9e4b0e..0ec7b7f1524b1263dfc80c8bc21aa698fed4b3de 100644 (file)
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -98,6 +98,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Cortex-A510     | #2051678        | ARM64_ERRATUM_2051678       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1d7036e10215d37850f422af039045307ecf85f9..f2b5a4abef215275a73581e2a9bc7f1fe817eea1 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -670,6 +670,16 @@ config ARM64_ERRATUM_1508412
 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
        bool
 
+config ARM64_ERRATUM_2051678
+       bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
+       help
+         This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
+         Affected Coretex-A510 might not respect the ordering rules for
+         hardware update of the page table's dirty bit. The workaround
+         is to not enable the feature on affected CPUs.
+
+         If unsure, say Y.
+
 config ARM64_ERRATUM_2119858
        bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
        default y

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index a46ab3b1c4d5f9e949dc3692bdebb5e470161fd0..e5f23dab1c8df8acc56a64d982cb065984167ecb 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1645,6 +1645,9 @@ static bool cpu_has_broken_dbm(void)
                MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
                /* Kryo4xx Silver (rdpe => r1p0) */
                MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_2051678
+               MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
 #endif
                {},
        };