phy: phy-rockchip-samsung-hdptx: Swap the definitions of LCPLL_REF and ROPLL_REF

According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097)
to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0
selects the ROPLL.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250205105157.580060-2-damon.ding@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 35d5b762e5c4ced2687fec82b60ce49b6727ca6c..dfcc37b1c8a6db4cef86090960156bad192dfc44 100644 (file)
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -94,8 +94,8 @@
 #define LCPLL_ALONE_MODE               BIT(1)
 /* CMN_REG(0097) */
 #define DIG_CLK_SEL                    BIT(1)
-#define ROPLL_REF                      BIT(1)
-#define LCPLL_REF                      0
+#define LCPLL_REF                      BIT(1)
+#define ROPLL_REF                      0
 /* CMN_REG(0099) */
 #define CMN_ROPLL_ALONE_MODE           BIT(2)
 #define ROPLL_ALONE_MODE               BIT(2)