return 0;
 }
+
+void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+       if (!hsw_crtc_supports_ips(crtc))
+               return;
+
+       if (IS_HASWELL(i915)) {
+               crtc_state->ips_enabled = intel_de_read(i915, IPS_CTL) & IPS_ENABLE;
+       } else {
+               /*
+                * We cannot readout IPS state on broadwell, set to
+                * true so we can set it to a defined state on first
+                * commit.
+                */
+               crtc_state->ips_enabled = true;
+       }
+}
 
 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
 int hsw_ips_compute_config(struct intel_atomic_state *state,
                           struct intel_crtc *crtc);
+void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
 
 #endif /* __HSW_IPS_H__ */
 
                        ilk_get_pfit_config(pipe_config);
        }
 
-       if (hsw_crtc_supports_ips(crtc)) {
-               if (IS_HASWELL(dev_priv))
-                       pipe_config->ips_enabled = intel_de_read(dev_priv,
-                                                                IPS_CTL) & IPS_ENABLE;
-               else {
-                       /*
-                        * We cannot readout IPS state on broadwell, set to
-                        * true so we can set it to a defined state on first
-                        * commit.
-                        */
-                       pipe_config->ips_enabled = true;
-               }
-       }
+       hsw_ips_get_config(pipe_config);
 
        if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
            !transcoder_is_dsi(pipe_config->cpu_transcoder)) {