Merge tag 'drm-next-2024-11-21' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie:
 "There's a lot of rework, the panic helper support is being added to
  more drivers, v3d gets support for HW superpages, scheduler
  documentation, drm client and video aperture reworks, some new
  MAINTAINERS added, amdgpu has the usual lots of IP refactors, Intel
  has some Pantherlake enablement and xe is getting some SRIOV bits, but
  just lots of stuff everywhere.

  core:
   - split DSC helpers from DP helpers
   - clang build fixes for drm/mm test
   - drop simple pipeline support for gem vram
   - document submission error signaling
   - move drm_rect to drm core module from kms helper
   - add default client setup to most drivers
   - move to video aperture helpers instead of drm ones

  tests:
   - new framebuffer tests

  ttm:
   - remove swapped and pinned BOs from TTM lru

  panic:
   - fix uninit spinlock
   - add ABGR2101010 support

  bridge:
   - add TI TDP158 support
   - use standard PM OPS

  dma-fence:
   - use read_trylock instead of read_lock to help lockdep

  scheduler:
   - add errno to sched start to report different errors
   - add locking to drm_sched_entity_modify_sched
   - improve documentation

  xe:
   - add drm_line_printer
   - lots of refactoring
   - Enable Xe2 + PES disaggregation
   - add new ARL PCI ID
   - SRIOV development work
   - fix exec unnecessary implicit fence
   - define and parse OA sync props
   - forcewake refactoring

  i915:
   - Enable BMG/LNL ultra joiner
   - Enable 10bpx + CCS scanout on ICL+, fp16/CCS on TGL+
   - use DSB for plane/color mgmt
   - Arrow lake PCI IDs
   - lots of i915/xe display refactoring
   - enable PXP GuC autoteardown
   - Pantherlake (PTL) Xe3 LPD display enablement
   - Allow fastset HDR infoframe changes
   - write DP source OUI for non-eDP sinks
   - share PCI IDs between i915 and xe

  amdgpu:
   - SDMA queue reset support
   - SMU 13.0.6, JPEG 4.0.3 updates
   - Initial runtime repartitioning support
   - rework IP structs for multiple IP instances
   - Fetch EDID from _DDC if available
   - SMU13 zero rpm user control
   - lots of fixes/cleanups

  amdkfd:
   - Increase event FIFO size
   - add topology cap flag for per queue reset

  msm:
   - DPU:
      - SA8775P support
      - (disabled by default) MSM8917, MSM8937, MSM8953 and MSM8996 support
      - Enable large framebuffer support
      - Drop MSM8998 and SDM845
   - DP:
      - SA8775P support
   - GPU:
      - a7xx preemption support
      - Adreno A663 support

  ast:
   - warn about unsupported TX chips

  ivpu:
   - add coredump
   - add pantherlake support

  rockchip:
   - 4K@60Hz display enablement
   - generate pll programming tables

  panthor:
   - add timestamp query API
   - add realtime group priority
   - add fdinfo support

  etnaviv:
   - improve handling of DMA address limits
   - improve GPU hangcheck

  exynos:
   - Decon Exynos7870 support

  mediatek:
   - add OF graph support

  omap:
   - locking fixes

  bochs:
   - convert to gem/shmem from simpledrm

  v3d:
   - support big/super pages
   - add gemfs

  vc4:
   - BCM2712 support refactoring
   - add YUV444 format support

  udmabuf:
   - folio related fixes

  nouveau:
   - add panic support on nv50+"

* tag 'drm-next-2024-11-21' of https://gitlab.freedesktop.org/drm/kernel: (1583 commits)
  drm/xe/guc: Fix dereference before NULL check
  drm/amd: Fix initialization mistake for NBIO 7.7.0
  Revert "drm/amd/display: parse umc_info or vram_info based on ASIC"
  drm/amd/display: Fix failure to read vram info due to static BP_RESULT
  drm/amdgpu: enable GTT fallback handling for dGPUs only
  drm/amd/amdgpu: limit single process inside MES
  drm/fourcc: add AMD_FMT_MOD_TILE_GFX9_4K_D_X
  drm/amdgpu/mes12: correct kiq unmap latency
  drm/amdgpu: Support vcn and jpeg error info parsing
  drm/amd : Update MES API header file for v11 & v12
  drm/amd/amdkfd: add/remove kfd queues on start/stop KFD scheduling
  drm/amdkfd: change kfd process kref count at creation
  drm/amdgpu: Cleanup shift coding style
  drm/amd/amdgpu: Increase MES log buffer to dump mes scratch data
  drm/amdgpu: Implement virt req_ras_err_count
  drm/amdgpu: VF Query RAS Caps from Host if supported
  drm/amdgpu: Add msg handlers for SRIOV RAS Telemetry
  drm/amdgpu: Update SRIOV Exchange Headers for RAS Telemetry Support
  drm/amd/display: 3.2.309
  drm/amd/display: Adjust VSDB parser for replay feature
  ...

diff --cc Documentation/devicetree/bindings/vendor-prefixes.yaml
Simple merge

diff --cc MAINTAINERS
Simple merge

diff --cc drivers/gpu/drm/bridge/tc358768.c
Simple merge

diff --cc drivers/gpu/drm/drm_panel_orientation_quirks.c
Simple merge

diff --cc drivers/gpu/drm/gma500/Kconfig
index 23b7c14de5e29238ece939d5822d8a9ffc4675cc,c2927c37c40b8772e5d533f7767b1b898ed929be..aa2ea128aa2fc74ef72cadf6150bd3c1c34b6c21
--- 1/drivers/gpu/drm/gma500/Kconfig
--- 2/drivers/gpu/drm/gma500/Kconfig
+++ b/drivers/gpu/drm/gma500/Kconfig
@@@ -1,7 -1,8 +1,8 @@@
  # SPDX-License-Identifier: GPL-2.0-only
  config DRM_GMA500
        tristate "Intel GMA500/600/3600/3650 KMS Framebuffer"
 -      depends on DRM && PCI && X86 && MMU
 +      depends on DRM && PCI && X86 && MMU && HAS_IOPORT
+       select DRM_CLIENT_SELECTION
        select DRM_KMS_HELPER
        select FB_IOMEM_HELPERS if DRM_FBDEV_EMULATION
        select I2C

diff --cc drivers/gpu/drm/i915/display/intel_tv.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
index aa0b1bfb38e0d93cb48439cde311ea04825bdce1,0f19cbd3682981fec8c32147511250eabe0d3b04..7b1a061d92fbf60d33016b29cae848a7c34e38e0
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -539,13 -536,10 +536,14 @@@ IS_SUBPLATFORM(const struct drm_i915_pr
   */
  #define IS_LUNARLAKE(i915) (0 && i915)
  #define IS_BATTLEMAGE(i915)  (0 && i915)
+ #define IS_PANTHERLAKE(i915) (0 && i915)
  
 -#define IS_ARROWLAKE(i915) \
 -      IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL)
 +#define IS_ARROWLAKE_H(i915) \
 +      IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H)
 +#define IS_ARROWLAKE_U(i915) \
 +      IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U)
 +#define IS_ARROWLAKE_S(i915) \
 +      IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S)
  #define IS_DG2_G10(i915) \
        IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
  #define IS_DG2_G11(i915) \

diff --cc drivers/gpu/drm/i915/intel_device_info.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_device_info.h
Simple merge

diff --cc drivers/gpu/drm/imagination/pvr_context.c
Simple merge

diff --cc drivers/gpu/drm/imagination/pvr_drv.c
Simple merge

diff --cc drivers/gpu/drm/imagination/pvr_vm.c
Simple merge

diff --cc drivers/gpu/drm/msm/adreno/adreno_gpu.c
Simple merge

diff --cc drivers/gpu/drm/panthor/panthor_mmu.c
Simple merge

diff --cc drivers/gpu/drm/qxl/Kconfig
index 17d6927e5e23402786117fd0f99186978956c1c2,1992df4a82d278cf46d7e192f72805b63623c1a3..98a148bea62886ec8d512cf3e4a05aaad991f846
--- 1/drivers/gpu/drm/qxl/Kconfig
--- 2/drivers/gpu/drm/qxl/Kconfig
+++ b/drivers/gpu/drm/qxl/Kconfig
@@@ -1,7 -1,8 +1,8 @@@
  # SPDX-License-Identifier: GPL-2.0-only
  config DRM_QXL
        tristate "QXL virtual GPU"
 -      depends on DRM && PCI && MMU
 +      depends on DRM && PCI && MMU && HAS_IOPORT
+       select DRM_CLIENT_SELECTION
        select DRM_KMS_HELPER
        select DRM_TTM
        select DRM_TTM_HELPER

diff --cc drivers/gpu/drm/tiny/bochs.c
index e738bb85831667f55c436e21e761435def113b9a,447989bb8201e83df91d24a35a77061ec4c00918..6f91ff1dbf7e2f7938031cbcb9c20a929b288795
--- 1/drivers/gpu/drm/tiny/bochs.c
--- 2/drivers/gpu/drm/tiny/bochs.c
+++ b/drivers/gpu/drm/tiny/bochs.c
@@@ -1,6 -1,6 +1,7 @@@
  // SPDX-License-Identifier: GPL-2.0-or-later
  
 +#include <linux/bug.h>
+ #include <linux/aperture.h>
  #include <linux/module.h>
  #include <linux/pci.h>
  
@@@ -94,13 -99,13 +100,18 @@@ struct bochs_device 
        struct drm_connector connector;
  };
  
+ static struct bochs_device *to_bochs_device(const struct drm_device *dev)
+ {
+       return container_of(dev, struct bochs_device, dev);
+ }
+ 
  /* ---------------------------------------------------------------------- */
  
 +static __always_inline bool bochs_uses_mmio(struct bochs_device *bochs)
 +{
 +      return !IS_ENABLED(CONFIG_HAS_IOPORT) || bochs->mmio;
 +}
 +
  static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
  {
        if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
@@@ -234,10 -236,10 +242,10 @@@ static int bochs_hw_init(struct bochs_d
                        DRM_ERROR("Cannot map mmio region\n");
                        return -ENOMEM;
                }
 -      } else {
 +      } else if (IS_ENABLED(CONFIG_HAS_IOPORT)) {
                ioaddr = VBE_DISPI_IOPORT_INDEX;
                iosize = 2;
-               if (!request_region(ioaddr, iosize, "bochs-drm")) {
+               if (!devm_request_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) {
                        DRM_ERROR("Cannot request ioports\n");
                        return -EBUSY;
                }

diff --cc drivers/gpu/drm/tiny/cirrus.c
Simple merge

diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
Simple merge

diff --cc drivers/gpu/drm/xe/Kconfig
Simple merge

diff --cc drivers/gpu/drm/xe/regs/xe_gt_regs.h
Simple merge

diff --cc drivers/gpu/drm/xe/tests/xe_bo.c
index 8dac069483e8fda9f2a41eaee209711bcd59cf0b,cd811aa2b2277712b2c43bee2dcadc4a187d9688..3e0ae40ebbd283a9bf60fa0bdd4a7e3d95cc00c5
--- 1/drivers/gpu/drm/xe/tests/xe_bo.c
--- 2/drivers/gpu/drm/xe/tests/xe_bo.c
+++ b/drivers/gpu/drm/xe/tests/xe_bo.c
@@@ -6,6 -6,13 +6,13 @@@
  #include <kunit/test.h>
  #include <kunit/visibility.h>
  
 -#include <linux/random.h>
+ #include <linux/iosys-map.h>
+ #include <linux/math64.h>
++#include <linux/prandom.h>
+ #include <linux/swap.h>
+ 
+ #include <uapi/linux/sysinfo.h>
+ 
  #include "tests/xe_kunit_helpers.h"
  #include "tests/xe_pci_test.h"
  #include "tests/xe_test.h"

diff --cc drivers/gpu/drm/xe/xe_bo.c
Simple merge

diff --cc drivers/gpu/drm/xe/xe_device.c
Simple merge

diff --cc drivers/gpu/drm/xe/xe_device.h
Simple merge

diff --cc drivers/gpu/drm/xe/xe_device_types.h
Simple merge

diff --cc drivers/gpu/drm/xe/xe_gt_ccs_mode.c
index ffcbd05671fc0f6b78edd52915b50367aa1510a3,9360ac4de489ed37a133ab0352a0c74c86fece2d..b6adfb9f203069e5d3bd748ecdef909d6c60f883
--- 1/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
--- 2/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
+++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
@@@ -68,13 -68,7 +68,13 @@@ static void __xe_gt_apply_ccs_mode(stru
                }
        }
  
-       xe_mmio_write32(gt, CCS_MODE, mode);
 +      /*
 +       * Mask bits need to be set for the register. Though only Xe2+
 +       * platforms require setting of mask bits, it won't harm for older
 +       * platforms as these bits are unused there.
 +       */
 +      mode |= CCS_MODE_CSLICE_0_3_MASK << 16;
+       xe_mmio_write32(&gt->mmio, CCS_MODE, mode);
  
        xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
                  mode, config, num_engines, num_slices);

diff --cc drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
Simple merge

diff --cc drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
Simple merge

diff --cc drivers/gpu/drm/xe/xe_guc_ct.c
Simple merge

diff --cc drivers/gpu/drm/xe/xe_guc_submit.c
Simple merge

diff --cc drivers/gpu/drm/xe/xe_oa.c
Simple merge

diff --cc include/drm/intel/pciids.h
index f35534522d333816512eefdfe930cc606b93753d,7632507af1660458e1c642ae09fd5a6f9bad3e34..32480b5563db3cef065248b4b2f64516c18f132d
--- 1/include/drm/intel/i915_pciids.h
--- 2/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@@ -772,25 -765,15 +765,24 @@@
        INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
  
  /* ARL */
 -#define INTEL_ARL_IDS(MACRO__, ...) \
 -      MACRO__(0x7D41, ## __VA_ARGS__), \
 +#define INTEL_ARL_H_IDS(MACRO__, ...) \
        MACRO__(0x7D51, ## __VA_ARGS__), \
 +      MACRO__(0x7DD1, ## __VA_ARGS__)
 +
 +#define INTEL_ARL_U_IDS(MACRO__, ...) \
 +      MACRO__(0x7D41, ## __VA_ARGS__) \
 +
 +#define INTEL_ARL_S_IDS(MACRO__, ...) \
        MACRO__(0x7D67, ## __VA_ARGS__), \
 -      MACRO__(0x7DD1, ## __VA_ARGS__), \
        MACRO__(0xB640, ## __VA_ARGS__)
  
 +#define INTEL_ARL_IDS(MACRO__, ...) \
 +      INTEL_ARL_H_IDS(MACRO__, ## __VA_ARGS__), \
 +      INTEL_ARL_U_IDS(MACRO__, ## __VA_ARGS__), \
 +      INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__)
 +
  /* MTL */
  #define INTEL_MTL_IDS(MACRO__, ...) \
-       INTEL_ARL_IDS(MACRO__, ## __VA_ARGS__), \
        MACRO__(0x7D40, ## __VA_ARGS__), \
        MACRO__(0x7D45, ## __VA_ARGS__), \
        MACRO__(0x7D55, ## __VA_ARGS__), \