Add decoder for Intel Dunnington CPUs

The code came almost as-is from mcelog.

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

diff --git a/Makefile.am b/Makefile.am
index 6edf2f2527b951d7f05ed668d330355a02472fe4..c7c40051990c9b9439e4c6d6a052c58019654ae4 100644 (file)
--- a/Makefile.am
+++ b/Makefile.am
@@ -12,7 +12,8 @@ if WITH_AER
 endif
 if WITH_MCE
    rasdaemon_SOURCES += ras-mce-handler.c mce-intel.c mce-amd-k8.c \
-                       bitfield.c mce-intel-p4-p6.c mce-intel-nehalem.c
+                       bitfield.c mce-intel-p4-p6.c mce-intel-nehalem.c \
+                       mce-intel-dunnington.c
 endif
 rasdaemon_LDADD = -lpthread $(SQLITE3_LIBS) libtrace/libtrace.a
 

diff --git a/mce-intel-dunnington.c b/mce-intel-dunnington.c
new file mode 100644 (file)
index 0000000..dd29ddd
--- /dev/null
+++ b/mce-intel-dunnington.c
@@ -0,0 +1,112 @@
+/*
+ * The code below came from Andi Kleen/Intel/SuSe mcelog code,
+ * released under GNU Public General License, v.2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <string.h>
+#include <stdio.h>
+
+#include "ras-mce-handler.h"
+#include "bitfield.h"
+
+/* Follows Intel IA32 SDM 3b Appendix E.2.1 ++ */
+
+static struct field dunnington_bus_status[] = {
+       SBITFIELD(16, "Parity error detected during FSB request phase"),
+       FIELD(17, NULL),
+       SBITFIELD(20, "Hard Failure response received for a local transaction"),
+       SBITFIELD(21, "Parity error on FSB response field detected"),
+       SBITFIELD(22, "Parity data error on inbound data detected"),
+       FIELD(23, NULL),
+       FIELD(25, NULL),
+       FIELD(28, NULL),
+       FIELD(31, NULL),
+       {}
+};
+
+static char *dnt_front_error[0xf] = {
+       [0x1] = "Inclusion error from core 0",
+       [0x2] = "Inclusion error from core 1",
+       [0x3] = "Write Exclusive error from core 0",
+       [0x4] = "Write Exclusive error from core 1",
+       [0x5] = "Inclusion error from FSB",
+       [0x6] = "SNP stall error from FSB",
+       [0x7] = "Write stall error from FSB",
+       [0x8] = "FSB Arbiter Timeout error",
+       [0xA] = "Inclusion error from core 2",
+       [0xB] = "Write exclusive error from core 2",
+};
+
+static char *dnt_int_error[0xf] = {
+       [0x2] = "Internal timeout error",
+       [0x3] = "Internal timeout error",
+       [0x4] = "Intel Cache Safe Technology Queue full error\n"
+               "or disabled ways in a set overflow",
+       [0x5] = "Quiet cycle timeout error (correctable)",
+};
+
+struct field dnt_int_status[] = {
+       FIELD(8, dnt_int_error),
+       {}
+};
+
+struct field dnt_front_status[] = {
+       FIELD(0, dnt_front_error),
+       {}
+};
+
+struct field dnt_cecc[] = {
+       SBITFIELD(1, "Correctable ECC event on outgoing core 0 data"),
+       SBITFIELD(2, "Correctable ECC event on outgoing core 1 data"),
+       SBITFIELD(3, "Correctable ECC event on outgoing core 2 data"),
+       {}
+};
+
+struct field dnt_uecc[] = {
+       SBITFIELD(1, "Uncorrectable ECC event on outgoing core 0 data"),
+       SBITFIELD(2, "Uncorrectable ECC event on outgoing core 1 data"),
+       SBITFIELD(3, "Uncorrectable ECC event on outgoing core 2 data"),
+       {}
+};
+
+static void dunnington_decode_bus(struct mce_event *e, uint64_t status)
+{
+       decode_bitfield(e, status, dunnington_bus_status);
+}
+
+static void dunnington_decode_internal(struct mce_event *e, uint64_t status)
+{
+       uint32_t mca = (status >> 16) & 0xffff;
+       if ((mca & 0xfff0) == 0)
+               decode_bitfield(e, mca, dnt_front_status);
+       else if ((mca & 0xf0ff) == 0)
+               decode_bitfield(e, mca, dnt_int_status);
+       else if ((mca & 0xfff0) == 0xc000)
+               decode_bitfield(e, mca, dnt_cecc);
+       else if ((mca & 0xfff0) == 0xe000)
+               decode_bitfield(e, mca, dnt_uecc);
+}
+
+void dunnington_decode_model(struct mce_event *e)
+{
+       uint64_t status = e->status;
+       if ((status & 0xffff) == 0xe0f)
+               dunnington_decode_bus(e, status);
+       else if ((status & 0xffff) == (1 << 10))
+               dunnington_decode_internal(e, status);
+}
+

diff --git a/mce-intel.c b/mce-intel.c
index 6b58d756e2fc2a1e4374356ea0233d57f6a79e81..4e489802218ae2a7539d7d85a6b8c5024c89f98c 100644 (file)
--- a/mce-intel.c
+++ b/mce-intel.c
@@ -362,10 +362,10 @@ int parse_intel_event(struct ras_events *ras, struct mce_event *e)
        case CPU_XEON75XX:
                xeon75xx_decode_model(e);
                break;
-#if 0
        case CPU_DUNNINGTON:
                dunnington_decode_model(e);
                break;
+#if 0
        case CPU_TULSA:
                tulsa_decode_model(e);
                break;

diff --git a/ras-mce-handler.h b/ras-mce-handler.h
index 4488ddcdcca17e15689eb90b42920a975d956c3a..65bfcbc9eeab6326a8860c0b0554bf9568aeef27 100644 (file)
--- a/ras-mce-handler.h
+++ b/ras-mce-handler.h
@@ -114,6 +114,7 @@ void core2_decode_model(struct mce_event *e);
 void p6old_decode_model(struct mce_event *e);
 void nehalem_decode_model(struct mce_event *e);
 void xeon75xx_decode_model(struct mce_event *e);
+void dunnington_decode_model(struct mce_event *e);
 
 /* Software defined banks */
 #define MCE_EXTENDED_BANK      128