#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
 #define FLEXCAN_IFLAG_RX_FIFO_WARN     BIT(6)
 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE        BIT(5)
-#define FLEXCAN_IFLAG_DEFAULT \
-       (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
-        FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
 
 /* FLEXCAN message buffers */
 #define FLEXCAN_MB_CODE_RX_INACTIVE    (0x0 << 24)
        struct flexcan_regs __iomem *regs;
        u32 reg_esr;
        u32 reg_ctrl_default;
+       u32 reg_imask1_default;
 
        struct clk *clk_ipg;
        struct clk *clk_per;
        if (work_done < quota) {
                napi_complete_done(napi, work_done);
                /* enable IRQs */
-               flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
+               flexcan_write(priv->reg_imask1_default, ®s->imask1);
                flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
        }
 
                 * save them for later use.
                 */
                priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
-               flexcan_write(FLEXCAN_IFLAG_DEFAULT &
+               flexcan_write(priv->reg_imask1_default &
                              ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
                flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
                              ®s->ctrl);
        /* enable interrupts atomically */
        disable_irq(dev->irq);
        flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
-       flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
+       flexcan_write(priv->reg_imask1_default, ®s->imask1);
        enable_irq(dev->irq);
 
        /* print chip status */
        priv->devtype_data = devtype_data;
        priv->reg_xceiver = reg_xceiver;
 
+       priv->reg_imask1_default = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
+               FLEXCAN_IFLAG_RX_FIFO_AVAILABLE |
+               FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID);
+
        netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
 
        platform_set_drvdata(pdev, dev);