dcr_write(msic->dcr_host, dcr_n, val);
 }
 
-static u32 msic_dcr_read(struct axon_msic *msic, unsigned int dcr_n)
-{
-       return dcr_read(msic->dcr_host, dcr_n);
-}
-
 static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
 {
        struct axon_msic *msic = get_irq_data(irq);
        u32 write_offset, msi;
        int idx;
 
-       write_offset = msic_dcr_read(msic, MSIC_WRITE_OFFSET_REG);
+       write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
        pr_debug("axon_msi: original write_offset 0x%x\n", write_offset);
 
        /* write_offset doesn't wrap properly, so we have to mask it */
        list_for_each_entry(msic, &axon_msic_list, list) {
                pr_debug("axon_msi: disabling %s\n",
                          msic->irq_host->of_node->full_name);
-               tmp  = msic_dcr_read(msic, MSIC_CTRL_REG);
+               tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
                tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
                msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
        }