u8 val;
        int ret;
        enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge;
+       enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode;
        enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity;
 
        lg_dbg("edge = %d, valid = %d\n", edge, valid);
 
        if (edge)
                val |= 0x08;
+       if (mode)
+               val |= 0x40;
        if (valid)
                val |= 0x01;
 
 
        LGDT3305_TPCLK_FALLING_EDGE = 1,
 };
 
+enum lgdt3305_tp_clock_mode {
+       LGDT3305_TPCLK_GATED = 0,
+       LGDT3305_TPCLK_FIXED = 1,
+};
+
 enum lgdt3305_tp_valid_polarity {
        LGDT3305_TP_VALID_LOW = 0,
        LGDT3305_TP_VALID_HIGH = 1,
 
        enum lgdt3305_mpeg_mode mpeg_mode;
        enum lgdt3305_tp_clock_edge tpclk_edge;
+       enum lgdt3305_tp_clock_mode tpclk_mode;
        enum lgdt3305_tp_valid_polarity tpvalid_polarity;
        enum lgdt_demod_chip_type demod_chip;
 };