PCI: dwc: Add a default pci_ops.map_bus for root port

The Designware root port config space is memory mapped accesses via the
DBI space by default. Add a common implementation
dw_pcie_own_conf_map_bus() for platforms to use.

Link: https://lore.kernel.org/r/20200821035420.380495-5-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index b626cc7cd43a501e011c271df671266df7dd0acc..feb3625f7d4d2bf9ff7b654762e59da66a3d803c 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -602,6 +602,18 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
        return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 }
 
+void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
+{
+       struct pcie_port *pp = bus->sysdata;
+       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+
+       if (PCI_SLOT(devfn) > 0)
+               return NULL;
+
+       return pci->dbi_base + where;
+}
+EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
+
 static struct pci_ops dw_pcie_ops = {
        .read = dw_pcie_rd_conf,
        .write = dw_pcie_wr_conf,

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 8b8ea5f3e7af850f945360ad6115ef67127f42dc..01345b8e4171bb32f398c60314ac8a13e3e3919b 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -377,6 +377,8 @@ void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 void dw_pcie_host_deinit(struct pcie_port *pp);
 int dw_pcie_allocate_domains(struct pcie_port *pp);
+void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,
+                                      int where);
 #else
 static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
@@ -408,6 +410,12 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
 {
        return 0;
 }
+static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus,
+                                                    unsigned int devfn,
+                                                    int where)
+{
+       return NULL;
+}
 #endif
 
 #ifdef CONFIG_PCIE_DW_EP