#define DDRMON_CH1_COUNT_NUM           0x3c
 #define DDRMON_CH1_DFI_ACCESS_NUM      0x40
 
+/**
+ * struct dmc_count_channel - structure to hold counter values from the DDR controller
+ * @access:       Number of read and write accesses
+ * @clock_cycles: DDR clock cycles
+ */
 struct dmc_count_channel {
        u32 access;
-       u32 total;
+       u32 clock_cycles;
 };
 
 struct dmc_count {
                        continue;
                count->c[i].access = readl_relaxed(dfi_regs +
                                DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
-               count->c[i].total = readl_relaxed(dfi_regs +
+               count->c[i].clock_cycles = readl_relaxed(dfi_regs +
                                DDRMON_CH0_COUNT_NUM + i * 20);
        }
 }
        struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
        struct dmc_count count;
        struct dmc_count *last = &dfi->last_event_count;
-       u32 access = 0, total = 0;
+       u32 access = 0, clock_cycles = 0;
        int i;
 
        rockchip_dfi_read_counters(dfi, &count);
 
        /* We can only report one channel, so find the busiest one */
        for (i = 0; i < dfi->max_channels; i++) {
-               u32 a, t;
+               u32 a, c;
 
                if (!(dfi->channel_mask & BIT(i)))
                        continue;
 
                a = count.c[i].access - last->c[i].access;
-               t = count.c[i].total - last->c[i].total;
+               c = count.c[i].clock_cycles - last->c[i].clock_cycles;
 
                if (a > access) {
                        access = a;
-                       total = t;
+                       clock_cycles = c;
                }
        }
 
        edata->load_count = access * 4;
-       edata->total_count = total;
+       edata->total_count = clock_cycles;
 
        dfi->last_event_count = count;