/* Saved cp0 stuff. */
        unsigned long cp0_status;
 
+#ifdef CONFIG_MIPS_FP_SUPPORT
        /* Saved fpu/fpu emulator stuff. */
        struct mips_fpu_struct fpu FPU_ALIGN;
+#endif
        /* Assigned branch delay slot 'emulation' frame */
        atomic_t bd_emu_frame;
        /* PC of the branch from a branch delay slot 'emulation' */
 #define FPAFF_INIT
 #endif /* CONFIG_MIPS_MT_FPAFF */
 
+#ifdef CONFIG_MIPS_FP_SUPPORT
+# define FPU_INIT                                              \
+       .fpu                    = {                             \
+               .fpr            = {{{0,},},},                   \
+               .fcr31          = 0,                            \
+               .msacsr         = 0,                            \
+       },
+#else
+# define FPU_INIT
+#endif
+
 #define INIT_THREAD  {                                         \
        /*                                                      \
         * Saved main processor registers                       \
        /*                                                      \
         * Saved FPU/FPU emulator stuff                         \
         */                                                     \
-       .fpu                    = {                             \
-               .fpr            = {{{0,},},},                   \
-               .fcr31          = 0,                            \
-               .msacsr         = 0,                            \
-       },                                                      \
+       FPU_INIT                                                \
        /*                                                      \
         * FPU affinity state (null if not FPAFF)               \
         */                                                     \
 
        OFFSET(THREAD_REG31, task_struct, thread.reg31);
        OFFSET(THREAD_STATUS, task_struct,
               thread.cp0_status);
-       OFFSET(THREAD_FPU, task_struct, thread.fpu);
 
        OFFSET(THREAD_BVADDR, task_struct, \
               thread.cp0_badvaddr);
        BLANK();
 }
 
+#ifdef CONFIG_MIPS_FP_SUPPORT
 void output_thread_fpu_defines(void)
 {
+       OFFSET(THREAD_FPU, task_struct, thread.fpu);
+
        OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
        OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
        OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
        OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
        BLANK();
 }
+#endif
 
 void output_mm_defines(void)
 {
 }
 #endif
 
+#ifdef CONFIG_MIPS_FP_SUPPORT
 void output_kvm_defines(void)
 {
        COMMENT(" KVM/MIPS Specific offsets. ");
        OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
        BLANK();
 }
+#endif
 
 #ifdef CONFIG_MIPS_CPS
 void output_cps_defines(void)