/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+ /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
+ /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+#else /* normal I/O port pins */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+#endif
+#endif
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* Check Board Identity:
*/
-int checkboard(void)
+int checkboard (void)
{
- printf("CPU86 (Rev %02x)\n", CPU86_REV);
- return 1;
+ printf ("CPU86 (Rev %02x)\n", CPU86_REV);
+ return 1;
}
/* ------------------------------------------------------------------------- */
* several times to try different SDRAM configurations on both
* 60x and local buses.
*/
-static long int try_init(volatile memctl8260_t *memctl, ulong sdmr, ulong orx,
- volatile uchar * base)
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+ ulong orx, volatile uchar * base)
{
- volatile uchar c = 0xff;
- ulong cnt, val;
- volatile ulong * addr;
- volatile uint * sdmr_ptr;
- volatile uint * orx_ptr;
- int i;
- ulong save[32]; /* to make test non-destructive */
- ulong maxsize;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff)) / 2;
-
- /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
- * we are configuring CS1 if base != 0
- */
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or2;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
+ volatile uchar c = 0xff;
+ ulong cnt, val;
+ volatile ulong *addr;
+ volatile uint *sdmr_ptr;
+ volatile uint *orx_ptr;
+ int i;
+ ulong save[32]; /* to make test non-destructive */
+ ulong maxsize;
+
+ /* We must be able to test a location outsize the maximum legal size
+ * to find out THAT we are outside; but this address still has to be
+ * mapped by the controller. That means, that the initial mapping has
+ * to be (at least) twice as large as the maximum expected size.
+ */
+ maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+ /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+ * we are configuring CS1 if base != 0
+ */
+ sdmr_ptr = &memctl->memc_psdmr;
+ orx_ptr = &memctl->memc_or2;
+
+ *orx_ptr = orx;
+
+ /*
+ * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+ *
+ * "At system reset, initialization software must set up the
+ * programmable parameters in the memory controller banks registers
+ * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+ * system software should execute the following initialization sequence
+ * for each SDRAM device.
+ *
+ * 1. Issue a PRECHARGE-ALL-BANKS command
+ * 2. Issue eight CBR REFRESH commands
+ * 3. Issue a MODE-SET command to initialize the mode register
+ *
+ * The initial commands are executed by setting P/LSDMR[OP] and
+ * accessing the SDRAM with a single-byte transaction."
+ *
+ * The appropriate BRx/ORx registers have already been set when we
+ * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ */
+
+ *sdmr_ptr = sdmr | PSDMR_OP_PREA;
*base = c;
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *base = c;
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
+ *sdmr_ptr = sdmr | PSDMR_OP_MRW;
+ *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
+ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *base = c;
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(cnt * sizeof(long) - 1);
- return (cnt * sizeof(long));
+ /*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+ i = 0;
+ for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+ addr = (volatile ulong *) base + cnt; /* pointer arith! */
+ save[i++] = *addr;
+ *addr = ~cnt;
}
- }
- return (maxsize);
+
+ addr = (volatile ulong *) base;
+ save[i] = *addr;
+ *addr = 0;
+
+ if ((val = *addr) != 0) {
+ *addr = save[i];
+ return (0);
+ }
+
+ for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+ addr = (volatile ulong *) base + cnt; /* pointer arith! */
+ val = *addr;
+ *addr = save[--i];
+ if (val != ~cnt) {
+ /* Write the actual size to ORx
+ */
+ *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
+ return (cnt * sizeof (long));
+ }
+ }
+ return (maxsize);
}
-long int initdram(int board_type)
+long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- long psize;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
- psize = 32 * 1024 * 1024;
+#ifndef CFG_RAMBOOT
+ ulong size8, size9;
+#endif
+ long psize;
+
+ psize = 32 * 1024 * 1024;
- memctl->memc_mptpr = CFG_MPTPR;
- memctl->memc_psrt = CFG_PSRT;
+ memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_psrt = CFG_PSRT;
#ifndef CFG_RAMBOOT
- /* 60x SDRAM setup:
- */
- psize = try_init(memctl, CFG_PSDMR, CFG_OR2_PRELIM,
- (uchar *) CFG_SDRAM_BASE);
-#endif /* CFG_RAMBOOT */
+ /* 60x SDRAM setup:
+ */
+ size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+ (uchar *) CFG_SDRAM_BASE);
+ size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+ (uchar *) CFG_SDRAM_BASE);
+
+ if (size8 < size9) {
+ psize = size9;
+ printf ("(60x:9COL) ");
+ } else {
+ psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+ (uchar *) CFG_SDRAM_BASE);
+ printf ("(60x:8COL) ");
+ }
+
+#endif /* CFG_RAMBOOT */
- icache_enable();
+ icache_enable ();
- return (psize);
+ return (psize);
}
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
-extern void doc_probe(ulong physadr);
+extern void doc_probe (ulong physadr);
void doc_init (void)
{
- doc_probe(CFG_DOC_BASE);
+ doc_probe (CFG_DOC_BASE);
}
#endif
/*
- * (C) Copyright 2000
- * Marius Groeger <mgroeger@sysgo.de>
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- *
- * (C) Copyright 2000
+ * (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Flash Routines for AM290[48]0B devices
+ * Flash Routines for Intel devices
*
*--------------------------------------------------------------------
* See file CREDITS for list of people who contributed to this
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#include <mpc8xx.h>
#include "cpu86.h"
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
- * Functions
*/
+ulong flash_int_get_size (volatile unsigned long *baseaddr,
+ flash_info_t * info)
+{
+ short i;
+ unsigned long flashtest_h, flashtest_l;
+
+ info->sector_count = info->size = 0;
+ info->flash_id = FLASH_UNKNOWN;
+
+ /* Write query command sequence and test FLASH answer
+ */
+ baseaddr[0] = 0x00980098;
+ baseaddr[1] = 0x00980098;
+
+ flashtest_h = baseaddr[0]; /* manufacturer ID */
+ flashtest_l = baseaddr[1];
+
+ if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+ return (0); /* no or unknown flash */
+
+ flashtest_h = baseaddr[2]; /* device ID */
+ flashtest_l = baseaddr[3];
+
+ if (flashtest_h != flashtest_l)
+ return (0);
+
+ switch (flashtest_h) {
+ case INTEL_ID_28F160C3B:
+ info->flash_id = FLASH_28F160C3B;
+ info->sector_count = 39;
+ info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
+ break;
+ case INTEL_ID_28F160F3B:
+ info->flash_id = FLASH_28F160F3B;
+ info->sector_count = 39;
+ info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
+ break;
+ default:
+ return (0); /* no or unknown flash */
+ }
+
+ info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+ if (info->flash_id & FLASH_BTYPE) {
+ volatile unsigned long *tmp = baseaddr;
+
+ /* set up sector start adress table (bottom sector type)
+ * AND unlock the sectors (if our chip is 160C3)
+ */
+ for (i = 0; i < info->sector_count; i++) {
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) {
+ tmp[0] = 0x00600060;
+ tmp[1] = 0x00600060;
+ tmp[0] = 0x00D000D0;
+ tmp[1] = 0x00D000D0;
+ }
+ info->start[i] = (uint) tmp;
+ tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */
+ }
+ }
+
+ memset (info->protect, 0, info->sector_count);
+
+ baseaddr[0] = 0x00FF00FF;
+ baseaddr[1] = 0x00FF00FF;
+
+ return (info->size);
+}
+
+static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
+{
+ short i;
+ uchar vendor, devid;
+ ulong base = (ulong)addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0x90;
+
+ udelay(1000);
+
+ vendor = addr[0];
+ devid = addr[1] & 0xff;
+
+ /* only support AMD */
+ if (vendor != 0x01) {
+ return 0;
+ }
+
+ vendor &= 0xf;
+ devid &= 0xff;
+
+ if (devid == AMD_ID_F040B) {
+ info->flash_id = vendor << 16 | devid;
+ info->sector_count = 8;
+ info->size = info->sector_count * 0x10000;
+ }
+ else if (devid == AMD_ID_F080B) {
+ info->flash_id = vendor << 16 | devid;
+ info->sector_count = 16;
+ info->size = 4 * info->sector_count * 0x10000;
+ }
+ else if (devid == AMD_ID_F016D) {
+ info->flash_id = vendor << 16 | devid;
+ info->sector_count = 32;
+ info->size = 4 * info->sector_count * 0x10000;
+ }
+ else {
+ printf ("## Unknown Flash Type: %02x\n", devid);
+ return 0;
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* sector base address */
+ info->start[i] = base + i * (info->size / info->sector_count);
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr = (volatile unsigned char *)(info->start[i]);
+ info->protect[i] = addr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_char *)info->start[0];
+ addr[0] = 0xF0; /* reset bank */
+ }
+
+ return (info->size);
+}
-static ulong flash_get_size (vu_char *addr, flash_info_t *info);
-static int write_byte (flash_info_t *info, ulong dest, uchar data);
/*-----------------------------------------------------------------------
*/
-
unsigned long flash_init (void)
{
- unsigned long size, totsize;
- int i;
- ulong addr;
-
- /* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Disable flash protection */
- CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
-
- totsize = 0;
- addr = CFG_FLASH_BASE;
- for(i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
- size = flash_get_size((vu_char *)addr, &flash_info[i]);
- if (flash_info[i].flash_id == FLASH_UNKNOWN)
- break;
- totsize += size;
- addr += size;
- }
+ unsigned long size_b0 = 0;
+ unsigned long size_b1 = 0;
+ int i;
+
+ /* Init: no FLASHes known
+ */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Disable flash protection */
+ CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
+
+ /* Static FLASH Bank configuration here (only one bank) */
+
+ size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]);
+ if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 >> 20);
+ }
+
+ size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]);
+ printf("(Bank#1 - %ld MB", size_b0 >> 20);
+
+ if (size_b1 > 0)
+ printf(", Bank#2 - %ld kB", size_b1 >> 10);
+
+ printf(")");
+
+ /* protect monitor and environment sectors
+ */
+
+#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE
+ if (size_b1) {
+ /* If PPCBoot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE
+ * but we shouldn't protect it.
+ */
+
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[1]
+ );
+ }
+#else
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
- &flash_info[0]);
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]
+ );
+#endif
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
- &flash_info[0]);
+# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE
+ if (size_b1) {
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
+ }
+# else
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+# endif
#endif
- return (totsize);
+ return (size_b0 + size_b1);
}
/*-----------------------------------------------------------------------
*/
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id >> 16) {
- case 0x1:
- printf ("AMD ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case AMD_ID_F040B:
- printf ("AM29F040B (4 Mbit)\n");
- break;
- case AMD_ID_F080B:
- printf ("AM29F080B (8 Mbit)\n");
- break;
- case AMD_ID_F016D:
- printf ("AM29F016D (16 Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_char *addr, flash_info_t *info)
+void flash_print_info (flash_info_t * info)
{
- short i;
- uchar vendor, devid;
- ulong base = (ulong)addr;
+ int i;
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x90;
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
- udelay(1000);
+ switch ((info->flash_id >> 16) & 0xff) {
+ case 0x89:
+ printf ("INTEL ");
+ break;
+ case 0x1:
+ printf ("AMD ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
- vendor = addr[0];
- devid = addr[1] & 0xff;
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F160C3B:
+ printf ("28F160C3B (16 Mbit, bottom sector)\n");
+ break;
+ case FLASH_28F160F3B:
+ printf ("28F160F3B (16 Mbit, bottom sector)\n");
+ break;
+ case AMD_ID_F040B:
+ printf ("AM29F040B (4 Mbit)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
- /* only support AMD */
- if (vendor != 0x01) {
- return 0;
- }
-
- vendor &= 0xf;
- devid &= 0xff;
-
- if (devid == AMD_ID_F040B) {
- info->flash_id = vendor << 16 | devid;
- info->sector_count = 8;
- info->size = info->sector_count * 0x10000;
- }
- else if (devid == AMD_ID_F080B) {
- info->flash_id = vendor << 16 | devid;
- info->sector_count = 16;
- info->size = 4 * info->sector_count * 0x10000;
- }
- else if (devid == AMD_ID_F016D) {
- info->flash_id = vendor << 16 | devid;
- info->sector_count = 32;
- info->size = 4 * info->sector_count * 0x10000;
- }
- else {
- printf ("## Unknown Flash Type: %02x\n", devid);
- return 0;
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* sector base address */
- info->start[i] = base + i * (info->size / info->sector_count);
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
- }
-
- return (info->size);
+ if (info->size < 0x100000)
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+ else
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
}
-
/*-----------------------------------------------------------------------
*/
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
{
- vu_char *addr = (vu_char *)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
+ vu_char *addr = (vu_char *)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
+ prot = 0;
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
} else {
- printf ("- no sectors to erase\n");
+ printf ("\n");
}
- return 1;
- }
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect]) {
- prot++;
+ /* Check the type of erased flash
+ */
+ if (info->flash_id >> 16 == 0x1) {
+ /* Erase AMD flash
+ */
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0x80;
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_char *)(info->start[sect]);
+ addr[0] = 0x30;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto AMD_DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (vu_char *)(info->start[l_sect]);
+ while ((addr[0] & 0x80) != 0x80) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+
+AMD_DONE:
+ /* reset to read mode */
+ addr = (volatile unsigned char *)info->start[0];
+ addr[0] = 0xF0; /* reset bank */
+
+ } else {
+ /* Erase Intel flash
+ */
+
+ /* Start erase on unprotected sectors
+ */
+ for (sect = s_first; sect <= s_last; sect++) {
+ volatile ulong *addr =
+ (volatile unsigned long *) info->start[sect];
+
+ start = get_timer (0);
+ last = start;
+ if (info->protect[sect] == 0) {
+ /* Disable interrupts which might cause a timeout here
+ */
+ flag = disable_interrupts ();
+
+ /* Erase the block
+ */
+ addr[0] = 0x00200020;
+ addr[1] = 0x00200020;
+ addr[0] = 0x00D000D0;
+ addr[1] = 0x00D000D0;
+
+ /* re-enable interrupts if necessary
+ */
+ if (flag)
+ enable_interrupts ();
+
+ /* wait at least 80us - let's wait 1 ms
+ */
+ udelay (1000);
+
+ last = start;
+ while ((addr[0] & 0x00800080) != 0x00800080 ||
+ (addr[1] & 0x00800080) != 0x00800080) {
+ if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout (erase suspended!)\n");
+ /* Suspend erase
+ */
+ addr[0] = 0x00B000B0;
+ addr[1] = 0x00B000B0;
+ goto DONE;
+ }
+ /* show that we're waiting
+ */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+ if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+ printf ("*** ERROR: erase failed!\n");
+ goto DONE;
+ }
+ }
+ /* Clear status register and reset to read mode
+ */
+ addr[0] = 0x00500050;
+ addr[1] = 0x00500050;
+ addr[0] = 0x00FF00FF;
+ addr[1] = 0x00FF00FF;
+ }
}
- }
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
+ printf (" done\n");
+
+DONE:
+ return 0;
+}
- l_sect = -1;
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong v;
+ int i, l, rc, cc = cnt, res = 0;
+
+ if (info->flash_id >> 16 == 0x1) {
+
+ /* Write to AMD 8-bit flash
+ */
+ while (cnt > 0) {
+ if ((rc = write_byte(info, addr, *src)) != 0) {
+ return (rc);
+ }
+ addr++;
+ src++;
+ cnt--;
+ }
+
+ return (0);
+ } else {
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x80;
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
+ /* Write to Intel 64-bit flash
+ */
+ for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+ l = (addr & 3);
+ addr &= ~3;
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
+ for (i = 0; i < 4; i++) {
+ v = (v << 8) + (i < l || i - l >= cc ?
+ *((unsigned char *) addr + i) : *src++);
+ }
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char *)(info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_char *)(info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
+ if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+ break;
+ }
}
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (volatile unsigned char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
- printf (" done\n");
- return 0;
+ return (res);
}
/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
+ * Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+ ulong data)
{
- int rc;
+ int flag, res = 0;
+ ulong start;
+
+ /* Check if Flash is (sufficiently) erased
+ */
+ if ((*addr & data) != data)
+ return (2);
+
+ /* Disable interrupts which might cause a timeout here
+ */
+ flag = disable_interrupts ();
+
+ *addr = 0x00400040;
+ *addr = data;
+
+ /* re-enable interrupts if necessary
+ */
+ if (flag)
+ enable_interrupts ();
+
+ start = get_timer (0);
+ while ((*addr & 0x00800080) != 0x00800080) {
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ /* Suspend program
+ */
+ *addr = 0x00B000B0;
+ res = 1;
+ goto OUT;
+ }
+ }
- while (cnt > 0) {
- if ((rc = write_byte(info, addr, *src)) != 0) {
- return (rc);
+ if (*addr & 0x00220022) {
+ printf ("*** ERROR: program failed!\n");
+ res = 1;
}
- addr++;
- src++;
- cnt--;
- }
- return (0);
+OUT:
+ /* Clear status register and reset to read mode
+ */
+ *addr = 0x00500050;
+ *addr = 0x00FF00FF;
+
+ return (res);
}
/*-----------------------------------------------------------------------
*/
static int write_byte (flash_info_t *info, ulong dest, uchar data)
{
- vu_char *addr = (vu_char *)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
-
- *((vu_char *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
+ vu_char *addr = (vu_char *)(info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_char *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0xA0;
+
+ *((vu_char *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
}
- }
- return (0);
+ return (0);
}
/*-----------------------------------------------------------------------
/*
* Software (bit-bang) I2C driver configuration
*/
-#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00000010)
-#define I2C_TRISTATE (iop->pdir &= ~0x00000010)
-#define I2C_READ ((iop->pdat & 0x00000010) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
- else iop->pdat &= ~0x00000010
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
- else iop->pdat &= ~0x00000020
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE (iop->pdir |= 0x00010000)
+#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
+#define I2C_READ ((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
+ else iop->pdat &= ~0x00010000
+#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
+ else iop->pdat &= ~0x00020000
+#define I2C_DELAY udelay(10) /* 1/4 I2C clock duration */
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
#define CONFIG_BOOT_BOOTROM /* BTMD jumpers are set to 1-2, 3-4 */
-#ifdef CONFIG_BOOT_BOOTROM
-# define CFG_BOOTROM_BASE 0xFFF00000
-# define CFG_BOOTROM_SIZE 0x00100000
-# define CFG_BFLASH_BASE 0xFF000000
-# define CFG_BFLASH_SIZE 0x00800000
-# define CFG_FLASH_BASE CFG_BOOTROM_BASE
-# define CFG_FLASH_SIZE CFG_BOOTROM_SIZE
-#else
-# define CFG_BOOTROM_BASE 0xFF000000
-# define CFG_BOOTROM_SIZE 0x00100000
-# define CFG_BFLASH_BASE 0xFF800000
-# define CFG_BFLASH_SIZE 0x00800000
-# define CFG_FLASH_BASE CFG_BFLASH_BASE
-# define CFG_FLASH_SIZE CFG_BFLASH_SIZE
-#endif
+#define CFG_BOOTROM_BASE 0xFF800000
+#define CFG_BOOTROM_SIZE 0x00080000
+#define CFG_FLASH_BASE 0xFF000000
+#define CFG_FLASH_SIZE 0x00800000
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
* defines for the various registers affected by the HRCW e.g. changing
* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
*/
-#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CS10PC01)
+#if defined(CONFIG_BOOT_BOOTROM)
+#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+ HRCW_BPS01 | HRCW_CS10PC01)
+#else
+#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
+#endif
/* no slaves so just fill with zeros */
#define CFG_HRCW_SLAVE1 0
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
-#define CFG_DEFAULT_IMMR 0x00010000
#define CFG_IMMR 0xF0000000
/*-----------------------------------------------------------------------
#define CFG_I2C_EEPROM_ADDR_LEN 1
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_ENV_OFFSET 0
#define CFG_ENV_SIZE 2048
#endif
*/
#define CFG_RCCR 0
+#define CFG_MIN_AM_MASK 0xC0000000
/*-----------------------------------------------------------------------
* MPTPR - Memory Refresh Timer Prescaler Register 10-18
*-----------------------------------------------------------------------
*/
-#define CFG_MPTPR 0x4000
+#define CFG_MPTPR 0x1F00
/*-----------------------------------------------------------------------
* PSRT - Refresh Timer Register 10-16
* PSRT - SDRAM Mode Register 10-10
*-----------------------------------------------------------------------
*/
-#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A10 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_1W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
+
+ /* SDRAM initialization values for 8-column chips
+ */
+#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A9 |\
+ ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
+ PSDMR_BSMA_A14_A16 |\
+ PSDMR_SDA10_PBI0_A10 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_1W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+
+ /* SDRAM initialization values for 9-column chips
+ */
+#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A7 |\
+ ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
+ PSDMR_BSMA_A13_A15 |\
+ PSDMR_SDA10_PBI0_A9 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_1W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
/*
* Init Memory Controller:
/* Bank 1 - FLASH
*/
-#define CFG_BR1_PRELIM ((CFG_BFLASH_BASE & BRx_BA_MSK) |\
+#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_GPCM_P |\
BRx_V)
-#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BFLASH_SIZE) |\
+#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_3_CLK |\
#else /* CONFIG_BOOT_BOOTROM */
/* Bank 0 - FLASH
*/
-#define CFG_BR0_PRELIM ((CFG_BFLASH_BASE & BRx_BA_MSK) |\
+#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_GPCM_P |\
BRx_V)
-#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BFLASH_SIZE) |\
+#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_3_CLK |\
BRx_MS_SDRAM_P |\
BRx_V)
-#define CFG_OR2_PRELIM ((~(CFG_SDRAM_MAX_SIZE-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_12)
+#define CFG_OR2_PRELIM CFG_OR2_9COL
+
+#define CFG_PSDMR CFG_PSDMR_9COL
#endif /* CFG_RAMBOOT */
/* Bank 3 - Dual Ported SRAM
projects / users / rw / ppcboot.git / commitdiff